SBOU282A December   2022  – March 2023 OPA928

 

  1.   Abstract
  2.   Trademarks
  3. 1Read This First
    1. 1.1 EVM Cleanliness Guidelines
  4. 2Overview
    1. 2.1 Guarding and Shielding
  5. 3Getting Started
    1. 3.1 Related Documentation From Texas Instruments
    2. 3.2 Electrostatic Discharge Caution
  6. 4EVM Circuit Description
    1. 4.1 High-Impedance Amplifier Circuit
    2. 4.2 Transimpedance Amplifier Circuit
      1. 4.2.1 Configure the TIA
      2. 4.2.2 TIA Functions
        1. 4.2.2.1 T-Switch
        2. 4.2.2.2 Guarded Diode Limiter
  7. 5Cleaning the EVM
    1. 5.1 Ultrasonic Wash
    2. 5.2 Manual Cleaning Procedure
  8. 6Schematic, PCB Layout, and Bill of Materials
    1. 6.1 EVM Schematic
    2. 6.2 PCB Layout
    3. 6.3 Bill of Materials

Guarded Diode Limiter

Diode limiter circuits are commonly implemented to prevent the output voltage from exceeding a certain level. These circuits are particularly useful in high-gain applications that are vulnerable to input transients, such as low-level current measurements. On the OPA928EVM, the default TIA configuration is set in a gain of 10,000,000,000 V/A by the 10-GΩ feedback resistor, RF. When using ±5-V supplies, input current spikes greater than 500 pA drive the TIA output into the rail, and feedback is lost.

A typical diode limiter protects a TIA from input overcurrent events by adding a parallel Zener diode in the feedback path. This diode provides an alternate path for large input currents when the output voltage reaches the reverse breakdown voltage of the diode. The reverse breakdown voltage is selected to be less than the maximum output voltage swing of the amplifier, so that the output clips before reaching the rail, and feedback is never lost. The downside of the typical diode limiter circuit is that the Zener diode introduces a leakage path back into the input traces. Instead, the circuit shown in Figure 4-8 takes advantage of the OPA928 internal guard buffer and the internal ESD protection to implement a guarded diode limiter.

The internal guard buffer maintains the input common-mode potential on both sides of the internal ESD diodes. In a fault condition, overcurrent is directed though the ESD diodes and Zener diode, D1, to the output. During normal operation, any leakage current through D1 is directed away from the high-impedance input traces as a load on the guard buffer.

Figure 4-8 Guarded Diode Limiter

To enable this feature on the OPA928EVM, install a shunt jumper at JP4. D1 has a reverse breakdown voltage of 3.6 V. Assuming a maximum voltage of 0.7 V across the internal ESD diodes during the fault condition, and 3.6 V across D1, by Kirchoff's law, the output is limited to a maximum of 4.3 V. To remove the limiter function from the TIA circuit, leave the shunt at JP4 uninstalled, which takes D1 out of the feedback path.