SCEA064A June   2019  – March 2021 2N7001T , SN74AXC4T245 , SN74AXC4T774 , TXB0104

 

  1.   Trademarks
  2. 1Introduction
  3. 2Common Interfaces and 2N7001T Implementation
    1. 2.1 General Purpose Input Output (GPIO)
  4. 3Serial Peripheral Interface (SPI)
    1. 3.1 Application – SPI
  5. 4Universal Asynchronous Receive Transmit (UART)
    1. 4.1 Application – UART
  6. 5Joint Test Access Group (JTAG)
    1. 5.1 Application – JTAG
  7. 6Additional Resources
  8. 7Revision History

Universal Asynchronous Receive Transmit (UART)

UART is an asynchronous, moderate speeds, full duplex communication interface with either two or four channels; TX (transmit), RX (receive), or RX ,RTS, CTS, and TX.

Communication occurs with a start bit being sent, the data line being pulled from high to low in the middle of a bit period. The start bit is followed by 8 bits of information and a stop bit, the data line going from a logic low to a logic high in the middle of a bit period. Certain communication protocols sometimes have a parity bit which confirms that the correct information was transferred. UART does not depend on a clock line because the receiver and transmitter will have internal clocks that can be set to a selected baud rate or bits per second (usually from 300 bps to 115 kbps) for transmission.

For the UART interfaces to operate appropriately between two devices that are at different voltages, for example 1.8 V to 3.3 V, two of the 2N7001T unidirectional level shifters can be used at each of the signal lines. Since the device can up translate or down translate, it can be used for the receive and transmit lines.

GUID-E1371452-4F75-4DB2-9D74-86E3CE9EA48B-low.gif Figure 4-1 Two-Wire UART Interface Using 2N7001T Device