SCLK034 December   2023 SN54SC2T74-SEP

PRODUCTION DATA  

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Device Information
    1. 1.1 Device Details
  5. 2Total Dose Test Setup
    1. 2.1 Test Overview
    2. 2.2 Test Description and Facilities
    3. 2.3 Test Setup Details
      1. 2.3.1 Bias Diagram
    4. 2.4 Test Configuration and Condition
  6. 3TID Characterization Test Results
    1. 3.1 TID Characterization Summary Results
    2. 3.2 Specification Compliance Matrix
  7. 4Reference Documents
  8. 5Appendix: HDR TID Report Data

1 Device Information

The SN54SC2T74-SEP contains two independent D-type positive-edge-triggered flip-flops. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2-V input to 1.8-V output or 1.8-V input to 3.3-V output.) Additionally, the 5-V tolerant input pins enable down translation (for example, 3.3-V to 2.5-V output). The SN54SC2T74-SEP is a pure CMOS device and therefore was tested at a High Dose Rate (HDR) for TID testing.