SDAA033 December   2025 LM65625-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PDLC Circuit Implementation
  6. 3Summary
  7. 4References

2 PDLC Circuit Implementation

For this application the output voltage varies between 1.6V and 57V at 60Hz. One of the main characteristics of the LM65625 is the minimum on-time 35ns (TYP) which allows for low duty cycle conversions at high switching frequencies when the output voltage is low. For this design, 400kHz was selected as operating switching frequency as 400KHz enables a small circuit size while maintaining constant PWM control without folding back the switching frequency. The LM65625 switching at 400KHz can effectively buck at both high and low duty cycles that this application requires during the VOUT_PK and VOUT_TROUGH phases.

The LM65625 Utilizes a peak current control scheme and since the output voltage is a sinusoidal waveform alternating between 1.6V and 57V the effective (RMS) output voltage is VOUT_PK / Sqrt(2) = 40V. Sizing the output components was done with consideration of the RMS output voltage. This avoids the design complexity of over-designing for low and high gain swings on the AC output voltage. However, note that the voltage rating of the capacitor must be compliant with AC V OUT_PK. In this example, 100V rated capacitors were selected. Bucks one and two must have identical circuitry. Counter-intuitively the design of the circuit does not need to follow Equation 1 for VOUT_PK because that can oversize the inductor for this application. Instead, because the voltage is sinusoidally oscillating, the RMS voltage can be used. In testing for this application there were no issues with subharmonic oscillations when either buck had a >50% duty cycle during the 60Hz sinusoidal cycle while switching at 400KHz. At higher frequencies, the minimum on time can be a concern for the low duty cycle required for VOUT_TROUGH. To solve this, to achieve the same magnitude for VPDLC_pk, VOUT_TROUGH and VOUT_pk can be raised by the same magnitude.

Equation 1. L M I N ≥ 0.47 ∙   V O U T _ r m s F S W

A novel approach was implemented using the LM65625 DC-DC converter to generate the AC output voltage for the PDLC. Two buck converters are connected in a bridge configuration to supply the PDLC. The feedback networks of each converter are fed with 60Hz sine waves, 180° out of phase. In this way, a ± 57V peak A.C. sine wave is generated across the display, providing about 40Vrms at 2A. Two LM65625 buck ICs were used to generate the sourcing and sinking requirements to power a 80W PDLC. The sine waves were generated by a function generator for this example, but 60Hz sine waves can be generated using any DAC sine wave generator such as the one from the TMS320F28027 microcontroller.

Figure 2-1 shows the simplified PLDC application using LM65625-Q1.

Application Schematic Figure 2-1 Application Schematic

A 47uH (XGL6060) inductor was chosen which allowed for stable and reliable design without compromising circuit size. For COUT, 22uF effective output capacitance was required. 2 x 10uF + 2.2uF MLCC output capacitors were selected using the equations below. I was set to 0.8A (30% of the full load), and again the rms value of VOUT is used where applicable.

Equation 2. V R ≅   ∆ I 8 ∙ F S W ∙ C O U T
Equation 3. ∆ I ≅   V I N - V O U T _ r m s ∙ V O U T _ r m s V I N ∙ F S W ∙ L
Feedback Circuitry Figure 2-2 Feedback Circuitry

The AC output waveform comes from the AC voltage applied on the FB voltage. Figure 5 shows how current flows through the feedback divider system to generate the VOUT_TROUGH and VOUT_pk for the system. As the AC signal decreases the current flowing through the AC resistor increases and the effective VOUT decreases. The buck regulator essentially acts as an amplifier for the smaller signal to become an AC voltage source. Below are a series of equations for how to set the values for the feedback resistor circuitry. VPDLC_pk is a system parameter set by the specification for the specific application. Generally, 100Kohm is a robust value to choose for RFBT. The VREF for LM65625 is 0.8V, but that value can vary from buck to buck.

Equation 4. V P D L C _ p k = V O U T _ p k - V O U T _ t r o u g h
Equation 5. R F B B = R F B T ∙   V R E F V O U T _ t r o u g h – V R E F
Equation 6. R E Q =   R F B B   | |   R F B B _ A C
Equation 7. R E Q = R F B T ∙   V R E F V O U T _ p k – V R E F
Equation 8. R F B B _ A C = V F B B ∙   R E Q V F B B – R E Q

Below shows the output waveforms of the output voltage from the bucks as well the inductor current. The design provides a stable 60Hz output voltage. Simulation software such as SIMPLIS is useful for providing quick results and for quickly checking if the design is stable.

Simulation Results Figure 2-3 Simulation Results

The application circuit was also verified to work in the lab. Two LM65645EVMs and a function generator were configured to test the design. Figure 2-4 shows that this type of topology can generate the PLDC’s required 60Hz voltage.

Lab Results Figure 2-4 Lab Results