SFFS757 February   2024 DLP4620S-Q1 , DLPC231S-Q1

 

  1.   1
  2. 1Introduction
    1.     Trademarks
  3. 2 DLP4620S-Q1 Chipset Functional Safety Capability
  4. 3Development Process for Management of Systematic Faults
    1. 3.1 TI New-Product Development Process
    2. 3.2 TI Functional Safety Development Process
  5. 4 DLP4620S-Q1 Chipset Overview
    1. 4.1 Targeted Applications
    2. 4.2 DLP4620S-Q1 Chipset Functional Safety Concept
      1. 4.2.1 Typical Hazards
      2. 4.2.2 Chipset Architecture
      3. 4.2.3 Built-In Self Tests
    3. 4.3 Functional Safety Constraints and Assumptions
  6. 5Description of Hardware Component Parts
    1. 5.1 Description of System Level Built In Self Test (BISTs)
  7. 6Management of Random Faults
    1. 6.1 Fault Reporting
      1. 6.1.1 HOST_IRQ
      2. 6.1.2 Error History
      3. 6.1.3 Fault Handling
    2. 6.2 Functional Safety Mechanism Categories
    3. 6.3 Description of Functional Safety Mechanisms
      1. 6.3.1 Video Path Protection
        1. 6.3.1.1 Video Input BISTs
        2. 6.3.1.2 Video Processing BISTs
        3. 6.3.1.3 Video Output BISTs
      2. 6.3.2 Illumination Control Protection
        1. 6.3.2.1 Communication Interface and Register Protection
        2. 6.3.2.2 LED Control Feedback Loop Protection
        3. 6.3.2.3 Data Load and Transfer Protection
        4. 6.3.2.4 Watchdogs and Clock Monitors
        5. 6.3.2.5 Voltage Monitors
  8.   A Summary of Recommended Functional Safety Mechanism Usage
  9.   B Distributed Developments
    1.     B.1 How the Functional Safety Lifecycle Applies to TI Functional Safety Products
    2.     B.2 Activities Performed by Texas Instruments
    3.     B.3 Information Provided
  10.   C Revision History

6.3.2.4 Watchdogs and Clock Monitors

The following watchdogs are used to monitor that the various blocks of the DLPC231S-Q1 are properly operating. This is critical to ensuring that the LED brightness levels and timings are being properly controlled.

  • [SM_29] TPS99000S-Q1 Clock Ratio Monitor: The TPS99000S-Q1 calculates the ratio between its internal clock and the external DLPC231S-Q1 clock input in order to validate proper frequency operation of the main DLPC231S-Q1 clock source. The DLPC231S-Q1 main application periodically reads this ratio. If the ratio is outside of the expected range, the test fails. Upon failure an error is logged.
  • [SM_30] DLPC231S-Q1 Processor Watchdog (WD1): The TPS99000S-Q1 monitors the DLPC231S-Q1 processor to make sure that it is continuously operating. The main application software periodically resets the watchdog timer within an allocated time window. If the watchdog signal is not received by the TPS99000S-Q1 during the time window, the test fails. Upon failure, the TPS99000S-Q1 will signal a park of the DMD and reset the chipset. The main application will read the reset cause from the TPS99000S-Q1 and assert HOST_IRQ during reset initialization.
  • [SM_31] DLPC231S-Q1 Sequencer Watchdog (WD2): The TPS99000S-Q1 monitors the SEQ_START signal that is generated by the sequencer at the beginning of each frame. If the signal is not received within approximately 7 frames, the TPS99000S-Q1 determines that the sequencer is not functioning properly. The TPS99000S-Q1 alerts the DLPC231S-Q1. The DLPC231S-Q1 will attempt to disable and re-enable the sequencer 3 times. If it is unsuccessful after 3 tries, and emergency shutdown will be executed and an error will be logged.
  • [SM_32] Sequencer Instruction Read Watchdog: During proper operation, the sequencer block constantly reads and executes instructions from the sequencer memory. The main application software sets a timer within which an instruction must be read from memory. The timer is reset every time an instruction is read. If an instruction is not read within the allocated time, the test fails. Upon failure, emergency shutdown will be executed and an error will be logged. This test is always active when an image is being displayed.
  • [SM_12] DMD Reset Instruction Watchdog: Checks that the DMD has accepted command to update mirror positions. A reset command from the DLPC231S-Q1 tells the DMD to update mirror positions. If this command is not executed, mirrors will remain in their current position. Upon successfully receiving a reset command the DMD returns an acknowledge message. If this is not received by the DLPC231S-Q1 within an acceptable time, this test fails. Upon failure, emergency shutdown will be executed and an error will be logged. This test is always active when an image is being displayed.