SFFS835 March 2024 AFE539F1-Q1
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a failure mode analysis (FMA) for the pins of the AFE539F1-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to ground (see Table 4-2)
- Pin open-circuited (see Table 4-3)
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to supply (see Table 4-5)
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Table 4-1 TI Classification of Failure
Effects
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality. |
| B | No device damage, but loss of functionality. |
| C | No device damage, but performance degradation. |
| D | No device damage, no impact to functionality or performance. |
Figure 4-1 shows the AFE539F1-Q1 pin diagram. For a detailed description of the device pins, see the Pin Configuration and Functions section in the AFE539F1-Q1 data sheet.
Figure 4-1 Pin DiagramFollowing are the assumptions of use and the device configuration assumed for the pin FMA in this section:
- All the pin FMA analysis are described based on Figure 1-1.
Table 4-2 Pin FMA for Device Pins
Short-Circuited to Ground
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| FB0 | 1 | ADC and PWM duty cycle performance degradation | C |
| AIN0 | 2 | Loss of ADC functionality and PWM output duty cycle is stuck to maximum duty cycle | B |
| NC | 3 | No change in functionality or performance | D |
| NC | 4 | No change in functionality or performance | D |
| NC/SDO | 5 | Loss of SDO functionality and read back data is not available | B |
| SCL/SYNC | 6 | Loss of communication with the device | B |
| A0/SDI | 7 | Loss of communication with the device | B |
| SDA/SCLK/PWM | 8 | Loss of communication and PWM functionality with the device | B |
| NC | 9 | No change in functionality or performance | D |
| NC | 10 | No change in functionality or performance | D |
| NC | 11 | No change in functionality or performance | D |
| NC | 12 | No change in functionality or performance | D |
| CAP | 13 | Loss of functionality, device enters short circuit protection, power consumption increases | B |
| AGND | 14 | No change in functionality or performance | D |
| VDD | 15 | Complete loss of functionality, no device damage | B |
| VREF/MODE | 16 | Loss of core DAC functionality and PWM mode | B |
Table 4-3 Pin FMA for Device Pins
Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| FB0 | 1 | ADC and PWM duty cycle performance degradation | C |
| AIN0 | 2 | ADC input is not available and PWM output duty cycle will be corrupted | B |
| NC | 3 | No change in functionality or performance | D |
| NC | 4 | No change in functionality or performance | D |
| NC/SDO | 5 | Loss of SDO functionality and read back data is not available | B |
| SCL/SYNC | 6 | Loss of communication with the device | B |
| A0/SDI | 7 | Loss of communication with the device | B |
| SDA/SCLK/PWM | 8 | Loss of communication and PWM functionality is not available | B |
| NC | 9 | No change in functionality or performance | D |
| NC | 10 | No change in functionality or performance | D |
| NC | 11 | No change in functionality or performance | D |
| NC | 12 | No change in functionality or performance | D |
| CAP | 13 | Open-circuited pin can cause damage to the low-voltage digital core and NVM supplied by the internal LDO | A |
| AGND | 14 | Complete loss of functionality, no device damage | B |
| VDD | 15 | Complete loss of functionality, no device damage | B |
| VREF/MODE | 16 | Loss of core DAC functionality and PWM mode | B |
Table 4-4 Pin FMA for Device Pins
Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|---|
| FB0 | 1 | VREF/MODE | Short to corner pin is not expected | D |
| AIN0 | ADC and PWM duty cycle performance degradation | C | ||
| AIN0 | 2 | FB0 | ADC and PWM duty cycle performance degradation | C |
| NC | No change in functionality or performance | D | ||
| NC | 3 | AIN0 | No change in functionality or performance | D |
| NC | No change in functionality or performance | D | ||
| NC | 4 | NC | No change in functionality or performance | D |
| NC/SDO | Short to corner pin is not expected | D | ||
| NC/SDO | 5 | NC | Short to corner pin is not expected | D |
| SCL/SYNC | Loss of communication with the device, SDO functionality and read back data is not available | B | ||
| SCL/SYNC | 6 | NC/SDO | Loss of communication with the device, SDO functionality and read back data is not available | B |
| A0/SDI | Loss of communication with the device | B | ||
| A0/SDI | 7 | SCL/SYNC | Loss of communication with the device | B |
| SDA/SCLK/PWM | Loss of communication and PWM functionality with the device | B | ||
| SDA/SCLK/PWM | 8 | A0/SDI | Loss of communication and PWM functionality with the device | B |
| NC | Short to corner pin is not expected | D | ||
| NC | 9 | SDA/SCLK/PWM | Short to corner pin is not expected | D |
| NC | No change in functionality or performance | D | ||
| NC | 10 | NC | No change in functionality or performance | D |
| NC | No change in functionality or performance | D | ||
| NC | 11 | NC | No change in functionality or performance | D |
| NC | No change in functionality or performance | D | ||
| NC | 12 | NC | No change in functionality or performance | D |
| CAP | Short to corner pin is not expected | D | ||
| CAP | 13 | NC | Short to corner pin is not expected | D |
| AGND | Device enters short circuit protection, power consumption increases | B | ||
| AGND | 14 | CAP | Device enters short circuit protection, power consumption increases | B |
| VDD | Complete loss of functionality, no device damage | B | ||
| VDD | 15 | AGND | Complete loss of functionality, no device damage | B |
| VREF/MODE | Loss of partial functionality that includes I2C/SPI communication with device, external reference mode and internal reference mode | B | ||
| VREF/MODE | 16 | VDD | Loss of partial functionality that includes I2C/SPI communication with device, external reference mode and internal reference mode | B |
| FB0 | Short to corner pin is not expected | D |
Table 4-5 Pin FMA for Device Pins
Short-Circuited to
supply
| Pin Name | Pin No. | Description of Potential Failure Effects | Failure Effect Class |
|---|---|---|---|
| FB0 | 1 | ADC and PWM duty cycle performance degradation | C |
| AIN0 | 2 | Loss of ADC functionality and PWM output duty cycle is stuck to minimum duty cycle | B |
| NC | 3 | No change in functionality or performance | D |
| NC | 4 | No change in functionality or performance | D |
| NC/SDO | 5 | Loss of SDO functionality and read back data will be corrupted | B |
| SCL/SYNC | 6 | Loss of communication with the device | B |
| A0/SDI | 7 | Loss of communication with the device | B |
| SDA/SCLK/PWM | 8 | Loss of communication and PWM functionality with the device | B |
| NC | 9 | No change in functionality or performance | D |
| NC | 10 | No change in functionality or performance | D |
| NC | 11 | No change in functionality or performance | D |
| NC | 12 | No change in functionality or performance | D |
| CAP | 13 | Shorting to VDD pin can cause damage to the low-voltage digital core and NVM supplied by the internal LDO | A |
| AGND | 14 | Complete loss of functionality, no device damage | B |
| VDD | 15 | No change in functionality or performance | D |
| VERF/MODE | 16 | Loss of partial functionality that includes I2C/SPI communication with device, external reference mode and internal reference mode | B |