Design Notes

The DACx3204 12-Bit, 10-Bit, and 8-Bit, Quad Voltage and Current Output Smart DACs With Auto-Detected I2C, PMBus™, or SPI Interface Data Sheet recommends using a 100nF decoupling capacitor for the VDD pin and a 1.5µF or greater bypass capacitor for the CAP pin. The CAP pin is connected to the internal LDO. Place these capacitors close to the device pins.
There are three reference options for the DAC53204:
1. An external reference of 1.7V to V_DD can be applied to the VREF pin of the device. Connect a 100nF capacitor between the VREF pin and the AGND pin when using the external reference. Use a pullup resistor to V_DD when the external reference is not used.
2. There is a precision 1.21V reference with ×1.5, ×2, ×3, and ×4 gain options.
3. V_DD can be used as a reference.
The nominal voltage of the SMPS is set by resistors R₁ and R₂. The SMPS uses an internal 600mV reference voltage at the FB pin to determine the voltage at the output. Calculate R₁ and R₂ using the following equations:
$R_{1} = \frac{V_{N O M I N A L} - V_{F B}}{I_{N O M I N A L}}$
$R_{2} = \frac{R_{1} \times V_{F B}}{V_{N O M I N A L} - V_{F B}}$
A nominal current of 100µA through R₁ and R₂ and 3.3V nominal output voltage is used. With these values the equations become:
$R_{1} = \frac{3.3 V - 0.6 V}{100 μ A} = 27 k Ω$
$R_{2} = \frac{27 k Ω \times 0.6 V}{3.3 V - 0.6 V} = 6 k Ω$
To achieve the desired margin, the DAC53204 must sink or source additional current through R₁. This current (I_MARGIN) is calculated by:
$I_{M A R G I N} = (\frac{V_{N O M I N A L} \times (1 + M A R G I N) - V_{F B}}{R_{1}}) - I_{N O M I N A L}$
For a ±10% margin, the equation becomes:
$I_{M A R G I N} = (\frac{3.3 V \times (1 + 0.10) - 0.6 V}{27 k Ω}) - 100 μ A = 12 μ A$
The voltage output of the DAC53204 is turned into a current through the series resistor R₃. R₃ is calculated by:
$R_{3} = \frac{V_{D A C} - V_{F B}}{I_{M A R G I N}}$
Avoid DAC codes near zero- and full-scale when determining the DAC output voltage range to avoid the zero- and full-scale errors at these codes. This design uses the internal 1.21V reference with a gain of ×1.5 giving a full-scale voltage of 1.82V. The DAC53204 has a max zero-code error of 15mV, so a 20mV minimum output is a safe choice. I_MARGIN is considered positive and is being sourced from the DAC when V_DAC > V_FB. I_MARGIN is considered negative and is being sunk by the DAC53204 when V_DAC < V_FB. R₃ is calculated to be 48.3kΩ:
$R_{3} = \frac{20 m V - 0.6 V}{- 12 μ A} = 48.3 k Ω$
The maximum output becomes:
$V_{D A C, M A X} = (R_{3} \times I_{M A R G I N}) + V_{F B}$
$V_{D A C, M A X} = (48.3 k Ω \times 12 μ A) + 0.6 V = 1.18 V$
The DAC codes for V_DAC,MAX and V_DAC,MIN are stored in the DAC-MARGIN-HIGH and DAC-MARGIN-LOW registers. The codes programmed to these registers, in decimal, is calculated using:
$D A C_M A R G I N_H I G H = \frac{V_{D A C, M A X}}{V_{R E F} \times G A I N} \times 1024$
$D A C_M A R G I N_L O W = \frac{V_{D A C, M I N}}{V_{R E F} \times G A I N} \times 1024$
The equations become:
$D A C_M A R G I N_H I G H = \frac{1.18 V}{1.21 V \times 1.5} \times 1024 = 665.7 d$
$D A C_M A R G I N_L O W = \frac{20 m V}{1.21 V \times 1.5} \times 1024 = 11.2 d$
This is rounded to 666d and 11d to give a V_DAC,MAX of 1.18V and a V_DAC,MIN of 19.5mV.
Using a 1.21V reference with a ×1.5 gain and the 10-bit DAC53204, the LSB size, or step size between each code, is about 1.8mV. Using lower reference voltages decreases the LSB size and thus increases the resolution of V_DAC,MAX and V_DAC,MIN.
In this design, GPI is used for Margin High, Low function. A high on GPI sets the DAC output to V_DAC,MAX and the SMPS V_OUT to margin low, or 2.97V. A low on GPI sets the DAC output to V_DAC,MIN and the SMPS V_OUT to margin high, or 3.63V.
The DAC53204 can be programmed with the initial register settings described in the Register Settings section using I²C or SPI. The initial register settings can be saved in the NVM by writing a 1 to the NVM-PROG field of the COMMON-TRIGGER register. After programming the NVM, the device loads all registers with the values stored in the NVM after a reset or a power cycle.