SLAAE33 September   2021 DAC43204 , DAC43401 , DAC43701 , DAC43701-Q1 , DAC53204 , DAC53401 , DAC53701 , DAC53701-Q1 , LM555 , LMC555 , NA555 , NE555 , SA555 , SE555 , TLC555

 

  1.   Trademarks
  2. 1Introduction
  3. 2Functional Overview of 555 Timers vs. Smart DACs
  4. 3Pulse Generator with Variable Frequency and Variable Duty Cycle
  5. 4Analog Input to PWM Output
  6. 5General Purpose Input (GPI) to PWM Output
  7. 6Comparator with Hysteresis
  8. 7Trade-offs and Conclusions

Functional Overview of 555 Timers vs. Smart DACs

A block diagram of the 555 timer is shown in Figure 2-1. It consists of an internal resistor divider between the supply voltage (VDD) and ground (GND) with each resistor equaling a nominal value of 100 kΩ. The THRESH and TRIG pins are direct inputs to the two input comparators and the CONT pin gives the user a direct input to the inverting input of the high comparator. The trigger levels of these two comparators are set to ⅓ × VDD and ⅔ × VDD due to the internal resistor divider made up of three equal resistors. Applying a voltage to the CONT pin changes the trigger levels to ½ × VCONT and VCONT. The outputs of the two comparators are fed to a flip-flop and the output of the flip-flop is sent to the base of an NPN transistor (in the case of a bipolar 555 timer) or gate of an NMOS transistor (in the case of a CMOS 555 timer) which functions as the discharge path of the device and is also sent through an inverter to the OUT pin. Therefore, when OUT is high, the discharge path between the DISCH pin and GND is disabled and when OUT is low, the discharge path is enabled. Collections of various external components can be used with these blocks to create many functional circuits.

Figure 2-1 Functional Block Diagram of a 555 Timer

A block diagram of the DAC53701 smart DAC is shown in Figure 2-2. A typical smart DAC consists of a I2C or SPI digital interface, a precision internal reference, and a string DAC. The internal voltage output buffer has an exposed feedback path available that can sense the output voltage. An additional feature common to smart DACs is non-volatile memory (NVM) which can store the register settings of the smart DAC for use in the field without a microcontroller. Smart DACs have general purpose input (GPI) pin handling that can be configured to control various register settings or output states. A power down logic block is included to set the output state of the smart DAC to modes such as high impedance (Hi-Z) power down, or 10-kΩ to GND power down. One final common feature of smart DACs is a continuous waveform generation (CWG) mode that can produce triangular, sawtooth, square, or sine waveforms. These features can be applied in circuits that will be discussed in the upcoming sections.

Figure 2-2 Functional Block Diagram of the DAC53701 Smart DAC