SLAAEE0 November   2023 TAC5111 , TAC5112 , TAC5211 , TAC5212 , TAC5412-Q1 , TAD5112 , TAD5212 , TAD5212-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Output Configuration
    1. 2.1 Common-mode Generation
    2. 2.2 Output Load Range for Line Output And Headphone
    3. 2.3 Mixing and Bypass
  6. 3Summary
  7. 4References

Introduction

The TAD5212-Q1 is a high-performance stereo DAC which supports 2-VRMS differential-ended and 1-VRMS single-ended input, as well as differential, pseudo-differential, and single-ended output.

The device consists of two pairs of analog output pins (OUTxP and OUTxM) that can be configured as differential outputs or single-ended outputs for playback channel. The device supports simultaneous playback of up to four channels of single-ended output or up to two channels of fully-differential or pseudo-differential output using the high-performance multichannel DAC.

The source of OUT1P and OUT1M can be selected with register 100 in Page 0. There are three bits (OUT1x_SRC[2:0]) that control the source for a specific path, for example code 011 is used for mixing of DAC output with analog bypass signal chains, and code 100 selects OUT1P of the DAC, and OUT1M for the analog bypass signal chain. These examples are among several available options. See also the TAD5212-Q1 data sheet for a complete list of available options for selection of the source for signal chain path for OUT1P and OUT1M. Similar to OUT1P and OUT1M, the OUT2x_SRC[2:0] bits in register 107 can be used to set the source for OUT2P and OUT2M.

The output channels for playback can be enabled or disabled by using register 118 (CH_EN) and the input channels for the audio serial interface can be enabled or disabled by using the PASI_RX_CHx_CFG or SASI_RX_CHx_CFG bits.

The TAD5212-Q1 device supports simultaneous power-up and power-down of all active channels for simultaneous playback. However, based on the application needs, if some channels must be powered-up or powered-down dynamically when the other channel playback is on, then that use case is supported by setting the DYN_PUPD_CFG register. Figure 1-1 shows the functional block diagram of internal components of the DAC.

GUID-20230614-SS0I-0BCM-HF2B-SC9SHPNJSNZT-low.svg Figure 1-1 Functional Block Diagram of Internal Components of the DAC