SLAAEQ5 March   2025 MSPM0C1103 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0C1105 , MSPM0C1106 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0H3216 , MSPM0L1105 , MSPM0L1106 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Cyber Security Requirement Introduction
    1. 1.1 Cyber Security Requirement for MSPM0
  5. 2MSPM0 Debug Register Introduction
  6. 3Implementation
    1. 3.1 Debugger with Mailbox
    2. 3.2 MCU
      1. 3.2.1 Usage and Configuration of Nonmain
      2. 3.2.2 MSPM0 Software Implementation
  7. 4Execution
    1. 4.1 First Time Flashing
    2. 4.2 Access to Locked MCU
  8. 5How to Customize Passwords
    1. 5.1 Password
    2. 5.2 Password Length
  9. 6Summary
  10. 7References

2 MSPM0 Debug Register Introduction

MSPM0 uses the ARM® M0+ core, allowing the user to follow the procedure described by ARM to switch the device from JTAG to SWD. Like the common ARM core, MSPM0 mainly uses the debugger to transmit data between AP and DP based on the SWD protocol to access the MCU internal.

MSPM0 devices support debugging of processor execution, the device state, and the power state (through EnergyTrace™ technology). The DEBUGSS also provides a mailbox system for communicating with software through SWD.

ARM Cortex devices Debug Block Diagram Figure 2-1 ARM Cortex devices Debug Block Diagram

Figure 2-1 shows MSPM0 Debug Sub System Block Diagram. MSPM0 devices support debugging of processor execution, the device state, and the power state (through EnergyTrace technology). The DEBUGSS also provides a mailbox system for communicating with software through SWD.

Debug Sub System Block Diagram Figure 2-2 Debug Sub System Block Diagram

The SWD physical interface interacts with the Arm serial wire debug port (SW-DP) to gain access to the debug access port bus interconnect (DAPBUSIC) when the SW-DP is enabled.

There are several debug access ports in the DEBUGSS.

Table 2-1 DEBUGSS Access Port Listing
AP Port Description Purpose
AHB-AP MCPUSS debug access port

Debug of the processor and peripherals
CFG-AP Configuration access port Access device type information, including the device part number and the device revision.
SEC-AP Security access port Access the debug subsystem mailbox(DSSM) for transmission of commands to the device during boot or communicating with software running on the device through SWD.
ET-AP EnergyTrace™ technology access port

Read the power state data from EnergyTrace technology for power aware

debug
PWR-AP Power access port Configure the device power states (interfaces with PMCU/SYSCTL), enabling low-power mode handling

The AHB-AP, PWR-AP, and ET-AP provide the complete device debug functionality (processor debug, peripheral and memory bus access, power state control, and processor state). And these can be disabled via BOOTCFG0 register in NONMAIN.