SLAS989D January   2014  – October 2017 ADC12J4000


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Internal Characteristics
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Signal Acquisition
      2. 7.3.2 The Analog Inputs
        1. Input Clamp
        2. AC Coupled Input Usage
        3. DC Coupled Input Usage
        4. Handling Single-Ended Input Signals
      3. 7.3.3 Clocking
      4. 7.3.4 Over-Range Function
      5. 7.3.5 ADC Core Features
        1. The Reference Voltage
        2. Common-Mode Voltage Generation
        3. Bias Current Generation
        4. Full Scale Range Adjust
        5. Offset Adjust
        6. Power-Down
        7. Built-In Temperature Monitor Diode
      6. 7.3.6 Digital Down Converter (DDC)
        1. NCO/Mixer
        2. NCO Settings
          1. NCO Frequency Phase Selection
          2. NCO_0, NCO_1, and NCO_2 (NCO_x)
          3. NCO_SEL Bits (2:0)
          4. NCO Frequency Setting (Eight Total)
            1. Basic NCO Frequency-Setting Mode
            2. Rational NCO Frequency Setting Mode
          5. NCO Phase-Offset Setting (Eight Total)
          6. Programmable DDC Delay
        3. Decimation Filters
        4. DDC Output Data
        5. Decimation Settings
          1. Decimation Factor
          2. DDC Gain Boost
      7. 7.3.7 Data Outputs
        1. The Digital Outputs
        2. JESD204B Interface Features and Settings
          1.  Scrambler Enable
          2.  Frames Per Multi-Frame (K-1)
          3.  DDR
          4.  JESD Enable
          5.  JESD Test Modes
          6.  Configurable Pre-Emphasis
          7.  Serial Output-Data Formatting
          8.  JESD204B Synchronization Features
          9.  SYSREF
          10. SYNC~
          11. Time Stamp
          12. Code-Group Synchronization
          13. Multiple ADC Synchronization
    4. 7.4 Device Functional Modes
      1. 7.4.1 DDC Bypass Mode
      2. 7.4.2 DDC Modes
      3. 7.4.3 Calibration
        1. Foreground Calibration Mode
        2. Background Calibration Mode
      4. 7.4.4 Timing Calibration Mode
      5. 7.4.5 Test-Pattern Modes
        1. ADC Test-Pattern Mode
        2. Serializer Test-Mode Details
        3. PRBS Test Modes
        4. Ramp Test Mode
        5. Short and Long-Transport Test Mode
        6. D21.5 Test Mode
        7. K28.5 Test Mode
        8. Repeated ILA Test Mode
        9. Modified RPAT Test Mode
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. Streaming Mode
    6. 7.6 Register Map
      1. 7.6.1 Memory Map
      2. 7.6.2 Register Descriptions
        1. Standard SPI-3.0 (0x000 to 0x00F)
          1. Configuration A Register (address = 0x000) [reset = 0x3C]
          2. Configuration B Register (address = 0x001) [reset = 0x00]
          3. Device Configuration Register (address = 0x002) [reset = 0x00]
          4. Chip Type Register (address = 0x003) [reset = 0x03]
          5. Chip Version Register (address = 0x006) [reset = 0x13]
          6. Vendor Identification Register (address = 0x00C to 0x00D) [reset = 0x0451]
        2. User SPI Configuration (0x010 to 0x01F)
          1. User SPI Configuration Register (address = 0x010) [reset = 0x00]
        3. General Analog, Bias, Band Gap, and Track and Hold (0x020 to 0x02F)
          1. Power-On Reset Register (address = 0x021) [reset = 0x00]
          2. I/O Gain 0 Register (address = 0x022) [reset = 0x40]
          3. IO_GAIN_1 Register (address = 0x023) [reset = 0x00]
          4. I/O Offset 0 Register (address = 0x025) [reset = 0x40]
          5. I/O Offset 1 Register (address = 0x026) [reset = 0x00]
        4. Clock (0x030 to 0x03F)
          1. Clock Generator Control 0 Register (address = 0x030) [reset = 0xC0]
          2. Clock Generator Status Register (address = 0x031) [reset = 0x07]
          3. Clock Generator Control 2 Register (address = 0x032) [reset = 0x80]
          4. Analog Miscellaneous Register (address = 0x033) [reset = 0xC3]
          5. Input Clamp Enable Register (address = 0x034) [reset = 0x2F]
        5. Serializer (0x040 to 0x04F)
          1. Serializer Configuration Register (address = 0x040) [reset = 0x04]
        6. ADC Calibration (0x050 to 0x1FF)
          1. Calibration Configuration 0 Register (address = 0x050) [reset = 0x06]
          2. Calibration Configuration 1 Register (address = 0x051) [reset = 0xF4]
          3. Calibration Background Control Register (address = 0x057) [reset = 0x10]
          4. ADC Pattern and Over-Range Enable Register (address = 0x058) [reset = 0x00]
          5. Calibration Vectors Register (address = 0x05A) [reset = 0x00]
          6. Calibration Status Register (address = 0x05B) [reset = undefined]
          7. Timing Calibration Register (address = 0x066) [reset = 0x02]
        7. Digital Down Converter and JESD204B (0x200-0x27F)
          1.  Digital Down-Converter (DDC) Control Register (address = 0x200) [reset = 0x10]
          2.  JESD204B Control 1 Register (address = 0x201) [reset = 0x0F]
          3.  JESD204B Control 2 Register (address = 0x202) [reset = 0x00]
          4.  JESD204B Device ID (DID) Register (address = 0x203) [reset = 0x00]
          5.  JESD204B Control 3 Register (address = 0x204) [reset = 0x00]
          6.  JESD204B and System Status Register (address = 0x205) [reset = Undefined]
          7.  Overrange Threshold 0 Register (address = 0x206) [reset = 0xF2]
          8.  Overrange Threshold 1 Register (address = 0x207) [reset = 0xAB]
          9.  Overrange Period Register (address = 0x208) [reset = 0x00]
          10. DDC Configuration Preset Mode Register (address = 0x20C) [reset = 0x00]
          11. DDC Configuration Preset Select Register (address = 0x20D) [reset = 0x00]
          12. Rational NCO Reference Divisor Register (address = 0x20E to 0x20F) [reset = 0x0000]
          13. NCO Frequency (Preset x) Register (address = see ) [reset = see ]
          14. NCO Phase (Preset x) Register (address = see ) [reset = see ]
          15. DDC Delay (Preset x) Register (address = see ) [reset = see ]
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 RF Sampling Receiver
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      2. 8.2.2 Oscilloscope
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
    3. 8.3 Initialization Set-Up
      1. 8.3.1 JESD204B Startup Sequence
    4. 8.4 Dos and Don'ts
      1. 8.4.1 Common Application Pitfalls
  9. Power Supply Recommendations
    1. 9.1 Supply Voltage
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Management
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
      3. 11.1.3 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resource
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Device and Documentation Support

Device Support

Third-Party Products Disclaimer


Development Support

For the ADC Harmonic Calculator, got to

Device Nomenclature

    Aperture (sampling) Delay is the amount of delay, measured from the sampling edge of the clock input, after which the signal present at the input pin is sampled inside the device.
    Aperture Jitter (t(AJ))is the variation in aperture delay from sample to sample. Aperture jitter appears as input noise.
    Clock Duty Cycle is the ratio of the time that the clock waveform is at a logic high to the total time of one clock period.
    Full Power Bandwidth (FPBW) is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below the low frequency value for a full scale input.
    Interleaving Spursare frequency domain (FFT) artifacts resulting from non-idealities in the multi-bank interleaved architecture of the ADC.
    Offset errors between banks result in fixed spurs at ƒS / 4 and ƒS / 2. Gain and timing errors result in input-signal-dependent spurs at ƒS / 4 ± FIN and ƒS / 2 ± FIN.
    Intermodulation Distortion (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. IMD is defined as the ratio of the power in the second-order and third-order intermodulation products to the power in one of the original frequencies. IMD is usually expressed in dBFS.
    Least Significant Bit (LSB ) is the bit that has the smallest value or weight of all bits. This value is calculated with Equation 18.
    Equation 18. VFS(dif) / 2n


    • VFS(dif) is the differential full-scale amplitude of VI as set by the FSR input (pin 14)
    • n is the ADC resolution in bits, which is 12 for the ADC12J4000 device
    CML Differential Output Voltage (VOD) is the absolute value of the difference between the positive and negative outputs. Each output is measured with respect to Ground.
    ADC12J4000 30180146.gif Figure 103. CML Output Signal Levels
    CML Output Offset Voltage (VO(ofs)) is the midpoint between the D+ and D– pins output voltage. Equation 19 is an example of VOS.
    Equation 19. [(VD+) + ( VD–)] / 2
    Most Significant Bit (MSB) is the bit that has the largest value or weight. The value of the MSB is one half of full scale.
    Overrange Recovery Time is the time required after the differential input voltages goes from ±1.2 V to 0 V for the converter to recover and make a conversion with its rated accuracy.
    Other Spurs is the sum of all higher harmonics (fourth and above), interleaving spurs, and any other fixed or input-dependent spurs.
    Data Delay (Latency) is the number of input clock cycles between initiation of conversion and when related data is present at the serializer output.
    Spurious-free Dynamic Range (SFDR)is the difference, expressed in dB, between the RMS values of the input signal at the output and the peak spurious signal, where a spurious signal is any signal present in the output spectrum that is not present at the input, excluding DC.
    Total Harmonic Distortion (THD)is the ratio expressed in dB, of the RMS total of the first nine harmonic levels at the output to the level of the fundamental at the output. THD is calculated with Equation 20.
    Equation 20. ADC12J4000 30180105.gif


    • A(f1) is the RMS power of the fundamental (output) frequency
    • A(f2) through A(f10) are the RMS power of the first nine harmonic frequencies in the output spectrum
    Second Harmonic Distortion (2nd Harm) is the difference, expressed in dB, between the RMS power in the input frequency detected at the output and the power in the second harmonic level at the output.
    Third Harmonic Distortion (3rd Harm) is the difference, expressed in dB, between the RMS power in the input frequency seen at the output and the power in the third harmonic level at the output.
    Word Error Rate is the probability of error and is defined as the probable number of errors per unit of time divided by the number of words seen in that amount of time. A Word Error Rate of 10–18 corresponds to a statistical error in one conversion about every four years.

Documentation Support

Related Documentation

For related documentation see the following:

  • LMH3401 7-GHz, Ultra-Wideband, Fixed-Gain, Fully-Differential Amplifier, SBOS695
  • LMK0482x Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs, SNAS605
  • LMX2581 Wideband Frequency Synthesizer with Integrated VCO, SNAS601
  • TRF3765 Integer-N/Fractional-N PLL with Integrated VCO, SLWS230

Community Resource

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Electrostatic Discharge Caution


These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.


SLYZ022TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.