SLLA605 april   2023 MCF8315A , MCF8316A

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Comparison Among the MCF8316A and MCF8315A
    1. 2.1 Hardware Comparison
    2. 2.2 Algorithm Features Comparison
    3. 2.3 EEPROM Register Map Comparison
    4. 2.4 RAM Register Map Comparison
    5. 2.5 RAM Algorithm Variable Register Map Comparison
  5. 3References

2.3 EEPROM Register Map Comparison

Table 2-3 EEPROM Register Map Comparison
Sl No. Register Field Name MCF8316A MCF8315A Comments Impact to MCF8316A customers moving to MCF8315A
1 Register: ISD_CONFIG
Bit Field: BRK_CONFIG
(Bit 20) 		Reserved Brake configuration
0h = Brake time is used to come out of Brake state
1h = Brake current threshold and Brake time is used to come out of Brake state		 New feature using current based brake during ISD for faster braking during start-up; reserved bits should be set to 0b in MCF8316A
  1. No impact if brake during ISD is not used
  2. No impact if time-based brake during ISD is used
  3. Same register settings as in MCF8316A can be used in MCF8315A if current based brake is not needed"
2 Register: ISD_CONFIG
Bit Field: BRK_CURR_THR
Bit 19:17		 Reserved Brake current threshold
Configurable from 0.0625 A to 5 A
3 Register: INT_ALGO_1
Bit Field: BRAKE_CURRENT_PERSIST
Bit 16:15		 Reserved Persistence time for current below threshold during low side brake
Configurable from 50 mS to 500 mS
4 REV_DRV_OPEN_LOOP_CURRENT 1.5 A to 5 A 0.9375 A to 3.125A Current scaled by 0.625 for MCF8315A Bit setting should be changed to maintain same/ similar current limit when changing to MCF8315A
5 ACTIVE_BRAKE_CURRENT_LIMIT 0.5 A to 7 A 0.3125A to 4.375 A
6 ALIGN_OR_SLOW_CURRENT_ILIMIT 0.125 A to 8 A 0.0781 A to 5 A
7 IPD_CURR_THR 0.25 A to 8 A 0.156 A to 5 A
8 OL_ILIMIT 0.125 A to 8 A 0.0781 A to 5 A
9 MPET_IPD_CURRENT_LIMIT 0.1 A to 2.0 A 0.0625 A to 1.25 A
10 MPET_OPEN_LOOP_CURRENT_REF 1 A to 8 A 0.0625 A to 5 A
11 CSA_GAIN 0 h = 0.15 V/A
1 h = 0.3 V/A
2 h = 0.6 V/A
3 h = 1.2 V/A		 0 h = 0.24 V/A
1 h = 0.48 V/A
2 h = 0.96 V/A
3 h = 1.92 V/A
12 ILIMIT: Reference for Torque PI Loop (A) 0.125 A to 8 A 0.0781 A to 5 A
13 HW_LOCK_ILIMIT 0.125 A to 8 A 0.0781 A to 5 A
14 LOCK_ILIMIT 0.125 A to 8 A 0.0781 A to 5 A
15 BUS_CURRENT_LIMIT 0.125 A to 8 A 0.0781 A to 5 A
16 NO_MTR_THR 0.05 A to 1 A 0.0312 A to 0.625 A
17 Register: PIN_CONFIG
Bit Field: VDC_FILT_DIS Bit: 27		 Reserved
Vdc filt is always enabled		 Vdc filter disable
0 h = Enable
1 h = Disable		 Additional feature
  1. No impact
  2. Use 0 h configuration to always enable Vdc filter
18 Register: PIN_CONFIG
Bit Field: FG_IDLE_CONFIG
Bit 10:9		 Not available FG Configuration During Stop
0h = FG continues and end state not defined, provided FG_CONFIG (defining FG during coasting)
1 h = FG is pulled High
2 h = FG is pulled Low
3 h = FG is pulled High		 Additional feature
  1. No impact
  2. Use 0 h configuration for backward compatibility
19 Register: PIN_CONFIG
Bit Field: FG_FAULT_CONFIG
Bit 8: 7		 Not available FG Configuration During Fault0h = Use last FG state when motor was driven
1 h = FG is pulled High
2 h = FG is pulled Low
3 h = FG active till BEMF drops below BEMF threshold defined by FG_BEMF_THR if FG_CONFIG set to 1b		 Additional feature
  1. No impact
  2. Use 0 h configuration for backward compatibility
20 Register: PIN_CONFIG
Bit Field: ALARM_PIN_EN
Bit 6		 Reserved
Not available		 Alarm Pin Enable
0 h = Disable
1 h = Enable		 Additional feature
  1. No impact
  2. For 0 h configuration alarm pin will be disabled
21 Register: PERI_CONFIG1
Bit Field: ALARM_PIN_DIS
Bit 8		 Not functional Reserved and replaced by ALARM_PIN_EN Changed EPROM location of the bit No impact
22 PIN_36_37_CONFIG Reserved Pin 36 and Pin 37 configuration
0 h = Pin 36 and Pin 37 are not defined as DAC pins
1 h = Pin 36 as DACOUT1 and PIN37 as DACOUT2		 Additional feature No impact
23 Register: INT_ALGO_1
Bit Field:
ACTIVE_BRAKE_SPEED__DELTA_LIMIT_EXIT
Bit 30:29		 Not available
(Bit no. 29 is used for FG_ANGLE_IN TERPOLATE_E N
Bit no. 30 is reserved)		 Configurable from 2.5% to 10 % Additional feature for configuring active braking exit limit
  1. No impact if active braking is not used
  2. Active braking exit limit configuration has to be chosen
24 ACTIVE_BRAKE_SPEED_DELTA_LIMIT 0 h = 2.5% 0 h = Reserved Active braking entry limit shall be always grater than exit limit. Hence configuration for 2.5% is removed
  1. Active braking speed entry limit configuration of 2.5% is removed
  2. Minimum possible entry limit is 5%
25 OCP_LVL 0 h = OCP level is 16 A (Typical)
1 h = OCP level is 24 A (Typical)		 0 h = OCP level is 9 A (Typical)
1 h = OCP level is 13 A (Typical)		 OCP levels are different for MCF8316 and MCF8315 OCP levels are to be selected as per need
26 Register: INT_ALGO_1
Bit Field: FG_ANGLE_IN TERPOLATE_EN
Bit 29		 Configurable Always Enabled
This bit is used to specify the active braking exit speed limit		 Minimizes tuning effort
  1. No impact
  2. This EPROM bit is used to select active braking exit limit
7 DAC_1 and DAC_2 registers Not available Available to configure DAC parameters Additional feature No impact
28 ABNORMAL_BEMF_THR 10% to 80% 40% to 70% Changed bit enumeration values for better resolution
  1. Use 011b in MCF8316A and tune if needed
  2. No impact - use same value as in MCF8316A
29 HW_LOCK_ILIMIT_DEG Configurable from 1 µS to 15 µS Configurable from 1 µS to 7 µS Additional bit in MCF8316A which was not applicable has been removed; set to 0100b in MCF8316A and 010b in MCF8315A for optimal performance
  1. No impact - use bit setting 0100b for MCF8316A and leave unchanged for MCF8315A for optimal performance
30 Duty Hysteresis Not available Duty hysteresis for speed reference mode New feature - added hysteresis for minimum duty cycle input
  1. No impact
  2. Hysteresis option at minimum duty cycle input threshold for MCF8315A
31 FIRST_CYCLE_FREQ_SEL 0 h = Defined by SLOW_FI RST_CYC_FREQ
1 h = 0 Hz		 0 h = 0 Hz
1 h = Defined by SLOW_FIRST_CYC_FREQ		 Bit enumeration definitions switched in MCF8316A data sheet No impact - use correct setting in MCF8316A tuning
32 MTR_STOP_BRK_TIME 0 h = 0.1 ms
1 h = 0.1 ms
2 h = 0.25 ms
3 h = 0.5 ms		 0 h = 1 ms
1 h = 1 ms
2 h = 1 ms
3 h = 1 ms		 Min possible brake time is 1ms; datasheet error in MCF8316A. No impact since setting any value lower than 0100b in MCF8316A results in 1ms brake time only
33 WD timer fault Not mentioned in data sheet Available Bit enumeration definitions not mentioned in MCF8316A datasheet No impact