SLLA673 March   2025 MCF8315A , MCF8315C , MCF8315D , MCF8316A , MCF8316C-Q1 , MCF8316D

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 MCF8315 Block Diagram and Pin Functions Introduction
  5. 2Fan Application Hardware Architecture
    1. 2.1 Total Discrete Hardware Design
    2. 2.2 MCU+Pre-Driver and External FET Design
    3. 2.3 All in One Design
  6. 3MCF8315 Hardware Design Guide for Fan Application
    1. 3.1 MCF8315 Power Part Design
    2. 3.2 MCF8315 Function Part Design
    3. 3.3 MCF8315 Communication and Output Part Design
    4. 3.4 MCF8315 Schematic Design Reference
    5. 3.5 MCF8315 Simplifies Peripheral Design
    6. 3.6 MCF8315 Thermal Performance Test
      1. 3.6.1 MCF8315 TSSOP Thermal Test With Inductance Version
  7. 4Summary
  8. 5References

1.1 MCF8315 Block Diagram and Pin Functions Introduction

Figure 1-1 is MCF8315 system block diagram and pin functions introduction.

MCF8315 Block DiagramFigure 1-1 MCF8315 Block Diagram
Table 1-1 MCF8315 Pin Functions
Power Part
PinTypeDescription
VMPWR5 to 40VIN voltage input
SW_BUCKPWRBuck switch node, connect this pin to an inductor or resistor
AVDDPWR O

Support 3.3V

3.3V LDO output, external 1uF capacitor to ground

This regulator can provide 20mA current to the external

(Need min 500nF effective capacitance across voltage and temperature. Can be 1uF or 2.2uF)

DVDDPWRExternal 1uF capacitor to ground (Need min 500nF effective capacitance across voltage and temperature. Can be 1uF or 2.2uF)
CPH,CPLPWRCharge pump switch node, connect a X7R, 47nF ceramic capacitor between the CPH and CPL pins, the recommendation that the rated voltage of the capacitor is at least twice the normal operating voltage of the device
CPPWRCharge pump output, connect a X7R, 1µF, 16V ceramic capacitor between the CP and VM pins
FB_BKPWR I/OThe feedback pin of the buck regulator output control, the buck regulator output after connecting the inductor/resistor. Aan also be provided by external LDO voltage/connected to AVDD,then the inductor/resistor of SW_BUCK can be omitted.

(Buck provides 4 different output voltage options: 3.3/4/5/5.7V)

Function Part
SPEED/ WAKEISpeed ​​command input, supports PWM/DUTY/VSP input

With an internal pull-down resistor of 1MΩ

FGOSpeed ​​output signal, open drain output
nFAULTOFault indication, pull down to low level under fault condition, PULLUP_ENABLE sets pull-up（ PULLUP_ENABLE enables internal pull-up to 3.3V and no external pull-up is needed when this feature is enabled）
DRVOFFI

DRVOFF is high level, and the six MOSFET outputs are in high impedance state.

If the DRVOFF pin is not used, connect directly to AGND (single point grounding).

If the DRVOFF pin is used to achieve MOSFET output high impedance state, connect an external 10k resistor to AGND for better noise suppression.

BRAKEI

High level → brake motor

Low level → normal motor operation

If the BRAKE pin is not used, connect directly to AGND (single point grounding).

DIRI

When low, the phase drive sequence is OUT A → OUT C → OUT B

When high, the phase drive sequence is OUT A → OUT B → OUT C

If DIR pin is not used, connect directly to AGND ,direction can be set using EEPROM setting

If DIR pin is used to change the motor rotation direction, connect an external 10k resistor to AGND for better noise suppression.

EXT_CLKI

External clock reference input in external clock reference mode

Speed ​​loop accuracy: 3% using internal clock, 1% using external clock reference(optional)

EXT_WDIExternal watchdog input(optional)
DACOUTODAC output
Communication Part
SCL/SDAI/OI2C clock & data
Motor Output Part
OUTA/B/CPWR OThree-phase U/V/W half-bridge motor output, no external current detection resistor required