SLLSEM7D January   2015  – January 2017 HD3SS460

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 High Speed Port Performance Parameters
    7. 7.7 High Speed Signal Path Switching Characteristics
    8. 7.8 Timing Diagrams
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 High Speed Differential Signal Switching
      2. 8.3.2 Low Speed SBU Signal Switching
      3. 8.3.3 Output Enable and Power Savings
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device High Speed Switch Control Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 USB SS and DP as Alternate Mode
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Critical Routing
      2. 11.1.2 General Routing/Placement Rules
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

6 Pin Configuration and Functions

RHR Package With Thermal Pad
(28-Pin WQFN)
Top View
HD3SS460 RHR_pinout_SLLSEM7.gif
RNH Package With Thermal Pad
(30-Pin WQFN)
Top View
HD3SS460 RNH_pinout_SLLSEM7.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME RHR
NO.		 RNH
NO.
VCC 22 23 P Power
GND PAD 13, 28, PAD G Ground
POL 3 3 Input Provides MUX control (Table 1)
AMSEL 8 8 3-Level Input Provides MUX configurations (Table 1)
EN 17 18 3-Level Input Enable signal; also provides MUX control (Table 1)
CRX1p, n 1, 2 1, 2 I/O High Speed Signal Port CRX1 positive, negative
CTX1p, n 4, 5 4, 5 I/O High Speed Signal Port CTX1 positive, negative
CTX2p, n 6, 7 6, 7 I/O High Speed Signal Port CTX2 positive, negative
CRX2p, n 9, 10 9, 10 I/O High Speed Signal Port CRX2 positive, negative
LnAn, p 15, 16 16, 17 I/O High Speed Signal Port LnA positive, negative
LnBn, p 18, 19 19, 20 I/O High Speed Signal Port LnB negative, positive
LnCn, p 20, 21 21, 22 I/O High Speed Signal Port LnC negative, positive
LnDn, p 23, 24 24, 25 I/O High Speed Signal Port LnD negative, positive
SSTXn, p 25, 26 26, 27 I/O High Speed Signal Port SSTX negative, positive
SSRXn, p 27, 28 29, 30 I/O High Speed Signal Port SSRX negative, positive
CSBU1, 2 11, 12 11, 12 I/O Low Speed Signal Port CSBU 1, 2
SBU1, 2 13, 14 14, 15 I/O Low Speed Signal Port SBU 1, 2
(1) High speed data ports (CRX[1/2][p/n], Ln[A-D][p,n], and SS[T/R]X[p/n]) incorporate 20kΩ pull down resistors that are switched in when a port is not selected and switched out when the port is selected.