SLLSEM7D January   2015  – January 2017 HD3SS460

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 High Speed Port Performance Parameters
    7. 7.7 High Speed Signal Path Switching Characteristics
    8. 7.8 Timing Diagrams
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 High Speed Differential Signal Switching
      2. 8.3.2 Low Speed SBU Signal Switching
      3. 8.3.3 Output Enable and Power Savings
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device High Speed Switch Control Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 USB SS and DP as Alternate Mode
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Critical Routing
      2. 11.1.2 General Routing/Placement Rules
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply Voltage, VCC –0.5 4 V
Differential High Speed I/O Voltages, C[R/T]X[1/2][p/n], Ln[A-D][p/n], SS[R/T]X[p/n] –0.5 2.5 V
Low Speed I/O Voltages, CSBU[1/2], SBU[1/2] –0.5 4 V
Control signal voltages, POL, AMSEL, EN –0.5 4 V
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 2.7 3.3 3.6 V
TA Operating free air temperature HD3SS460 0 25 70 °C
HD3SS460I –40 25 85
VCM High speed port common mode voltage 0 2 V
VIN Low Speed signal voltage 0 VCC
Vdiff High speed port differential voltage 0 1.8 Vpp

7.4 Thermal Information

THERMAL METRIC(1) HD3SS460 UNIT
QFN (RNH) QFN (RHR)
30 PINS 28 PINS
RθJA Junction-to-ambient thermal resistance 51.6 44.0 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 37.5 34.8 °C/W
RθJB Junction-to-board thermal resistance 17.5 14.7 °C/W
ψJT Junction-to-top characterization parameter 0.7 0.7 °C/W
ψJB Junction-to-board characterization parameter 17.3 24.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 6.8 6.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

typical values for all parameters are at VDD = 3.3 V and TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIL Input low voltage, control pins POL, AMSEL, EN –0.1 0.4 V
VIH Input high voltage, control pins AMSEL, EN VCC –0.4 VCC +0.1
Input high voltage, control pins POL 1.7 VCC +0.1
VIM Input mid-level voltage, control pins AMSEL, EN VCC/2 –0.3 VCC/2 VCC/2 +0.3
ILK-DIFF-ACTIVE Leakage current on active differential IO pins, VCC = 3.6 V, pin at 0 or 2.4 V. 1 µA
ILK-DIFF-INACTIVE Leakage current on inactive differential IO pins, VCC = 3.6V, pin at 2.4 V. 150
IIH Input high current, control pins POL, AMSEL, EN and signal pins CSBU1/2, SBU1/2 1
IIL Input low current, control pins POL, AMSEL, EN and signal pins CSBU1/2, SBU1/2 1
IIM Input mid-level current, control pins AMSEL, EN 1
IOFF Device shutdown current 1 5
IDD Device active current, EN=H or M 0.6 0.9 mA
RON(HS) Switch ON resistance for high speed differential signals VCC = 3.3 V, VCM = 0-2 V,
IO = - 8 mA		 8 14 Ω
RON(LS) Switch ON resistance for low speed signals VCC = 3.3 V, VCM = 0-2 V,
IO = - 8 mA		 12
RFLAT(ON,HS) High speed differential signals’ ON resistance flatness for a channel (RON(MAX) – RON(MIN)) over VCM range VCC = 3.3 V, VCM = 0-2 V,
IO = - 8 mA		 1.5
CON(HS) High speed differential signals’ input capacitance 1 pF

7.6 High Speed Port Performance Parameters

under recommended operating conditions; RLOAD, RSC = 50 Ω (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
RL Differential return loss 100 Mhz SS Paths –23 dB
2.5 Ghz SS Paths –9
100 MHz AM Paths –23
2. 7GHz AM Paths –13
IL Differential insertion loss 100 Mhz SS Paths –0.7
2.5 Ghz SS Paths –1.6
100 MHz AM Paths –0.7
2.7 GHz AM Paths –1.4
OI Differential off isolation 100 Mhz –50
2.5 Ghz –26
2.7 GHz –25
Xtalk Differential cross talk, Between CRX1/2 and CTX1/2 100 Mhz –80
2.5 Ghz –30
2.7 Ghz –28
Differential cross talk, Between CRX1 and CRX2 or CTX1 and CTX2 100 Mhz –50
2.5 Ghz –26
2.7 Ghz –25
BWSS Differential –3 dB BW SS Paths 4.2 GHz
BWAM Differential –3 dB BW AM Paths 5.4
BWSBU Low-speed switch –3 dB BW 500 MHz

7.7 High Speed Signal Path Switching Characteristics

PARAMETER TEST CONDITION MIN TYP MAX UNIT
tPD Switch propagation delay RSC and RLOAD = 50 Ω, Figure 2 100 ps
tSK(O) Inter-Pair output skew (CH-CH) 50
tSK(b-b) Intra-Pair output skew (bit-bit) 5
tON Control signals POL, AMSEL and EN (H/M toggle) to switch ON time RSC and RLOAD = 50 Ω, Figure 1 3 µs
tOFF Control signals POL, AMSEL and EN (H/M toggle) to switch OFF time 1

7.8 Timing Diagrams

HD3SS460 Switch_on-off_time_SLLSEM7.gif Figure 1. Switch ON/OFF Time
HD3SS460 Prop_delay_skew1_SLLSEM7.gif Figure 2. Propagation Delay and Skew