SLUAA16A August   2020  – October 2023 BQ79600-Q1

 

  1.   1
  2.   BQ79600-Q1 Design Recommendations
  3.   Trademarks
  4. 1Circuit Design
    1. 1.1 Power Supply (BAT, CVDD, DVDD, VIO pins)
    2. 1.2 Inhibit Output (INH pin)
    3. 1.3 Communication to Host (MOSI/RX, MISO/TX, nCS, SCLK, nUART/SPI (SPI_RDY) pins)
    4. 1.4 Fault Output (NFAULT pin)
    5. 1.5 Communication to Battery Monitor Device (COMHP, COMHN, COMLP, COMLN pins)
  5. 2Layout Guidelines
    1. 2.1 Ground Planes
    2. 2.2 Bypass Capacitors for Power Supplies and References
    3. 2.3 UART/SPI Communication
    4. 2.4 Daisy Chain Communication
  6. 3Daisy Chain Signal Integrity
    1. 3.1 Daisy Chain Receiver Threshold
    2. 3.2 Common and Differential Mode Noise
    3. 3.3 BCI Performance
    4. 3.4 Radiated Emissions Performance
  7. 4Summary
  8. 5References
  9. 6Revision History

1.4 Fault Output (NFAULT pin)

NFAULT pin is an active low fault indicator that, in the event of a fault, will pull low to signal to the host that a fault has occurred. nFAULT is an open drain active low pin, and therefore it needs to be pulled up to VIO with a 100 KΩ resistor. Connect nFAULT to a GPIO on the host MCU. If not used, connect to GND. See Figure 1-3 with recommended NFAULT connection.