SLUAAM4 December   2023 BQ76905 , BQ76907

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Direct Commands
    1. 1.1 Alarm Enable - 0x66
    2. 1.2 Cell 1 Voltage - 0x14
    3. 1.3 Internal Temperature - 0x28
    4. 1.4 CC2 Current - 0x3A
    5. 1.5 Direct Command Summary
      1. 1.5.1 Disabling Auto Refresh
  5. 2Subcommands
    1. 2.1 DEVICE_NUMBER - 0x0001
    2. 2.2 FET_ENABLE - 0x0022
    3. 2.3 RESET - 0x0012
    4. 2.4 CB_ACTIVE_CELLS - 0x0083
    5. 2.5 Subcommand Summary
  6. 3Reading and Writing RAM Registers
    1. 3.1 Read Enabled Protections A
    2. 3.2 Enter CONFIG_UPDATE Mode
    3. 3.3 Write Enabled Protections A
    4. 3.4 Write VCell Mode
    5. 3.5 Exit CONFIG_UPDATE Mode
    6. 3.6 Reading and Writing RAM Registers Summary
  7. 4I2C With CRC
  8. 5Simple Code Examples
  9. 6References

1.1 Alarm Enable - 0x66

Table 3-9 shows the Alarm Enable command that uses command 0x66. By default, the register setting for Alarm Enable is set to 0xC200. In Figure 1-1, the setting is changed to 0x0060. The data is in little endian format. The device address for the BQ7690x is 0x10 (8-bits) where the LSB is the R/W bit. A direct command follows the format I2C_Write(I2C_ADDR, Command, DataBlock), so for this example, the command can be I2C_Write(0x10, 0x66, [0x60, 0x00]).

Table 1-1 Alarm Enable Command Description
CommandNameUnitsTypeDescription
0x66Alarm EnableHexH2Mask for Alarm Status(). Can be written to change during operation to change which alarm sources are enabled.
GUID-20220817-SS0I-BMSR-HTJT-V9LRZJCRSXQG-low.png Figure 1-1 Captured I2C Waveform for Setting Alarm Enable to 0x0060