Figure 5-23 shows the effect of mismatched bias loading at startup where the load on VEE-COM is greater than the load on VDD-COM. A fixed resistive overload of 51.1-Ω (approximately 313 mW) is applied to VEE-COM while VDD-COM is left unloaded. VDD-VEE is regulating at 22-V, as expected but VDD-COM is measuring 21 V (needs to be 18 V) and VEE-COM is measuring 2 V (needs to be 4 V). Since VDD-COM is not directly monitored by feedback, over-voltage protection (OVP) is not triggered even though the measured voltage is 17% above the target value. Also, since VEE-COM is overloaded, the regulated voltage is only reaching 2 V which is 50% below the targeted set value of 4 V, therefore, VEE-COM UVLO is triggered. RLIM is internally switched to VDD (22 V) and is attempting to overcome the imbalance by sourcing current into the capacitor midpoint, COM connection. FBVDD and FBVEE must both be between 90%-110% of their target set value before 28.4 ms soft-start time as defined by the internal watch-dog-timer. The 28.4-ms, watch-dog-timer UVLO fault protection is enabled to protect the UCC14141-Q1 from output short-circuit or soft overload conditions. Once the UVLO fault is triggered, RLIM is internally switched to VEE, helping to discharge the outputs. When activated, as illustrated in Figure 5-23, the outputs are latched off into a protected sate. EN or VIN must be recycled to clear the UVLO fault and attempt to restart the module.