SLUUDE4 User guide

SLUUDE4 November 2025 LMK3H2108

1.1 LMK3H2108A01 Configuration Information

Table 1-1 LMK3H2108A01 Freuqency Configuration

OTP Page	OUT0 (MHz)	OUT1 (MHz)	OUT2 (MHz)	OUT3 (MHz)	OUT4 (MHz)	OUT5 (MHz)	OUT6 (MHz)	OUT7 (MHz)
OTP Page 0	100	100	100	100	100	100	100	100
OTP Page 1	100	100	100	100	100	100	100	100
OTP Page 2	100	100	100	100	100	100	100	100
OTP Page 3	100	100	100	100	100	100	100	100

Table 1-2 LMK3H2108A01 I2C Configuration

OTP Page	I2C Configuration
OTP Page 0	I2C Address: 0x9 1 Byte Register Addressing
OTP Page 1	I2C Address: 0x9 1 Byte Register Addressing
OTP Page 2	I2C Address: 0x9 1 Byte Register Addressing
OTP Page 3	I2C Address: 0x9 1 Byte Register Addressing

Table 1-3 LMK3H2108A01 GPI Settings, OTP Page 0

GPI Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPI0	GPI	Normal	Disabled	Disabled
GPI1	GPI	Normal	Disabled	Disabled
GPI2	GPI	Normal	Disabled	Disabled
GPI3	GPI	Normal	Disabled	Disabled
GPI4	GPI	Normal	Disabled	Disabled
GPI5	GPI	Normal	Disabled	Disabled

Table 1-4 LMK3H2108A01 GPIO Settings, OTP Page 0

GPIO Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPIO0	Dynamic OTP	Normal	Disabled	Disabled
GPIO1	Group OE, OE_GROUP_7	Normal	Disabled	Enabled
GPIO2	Dynamic OTP	Normal	Disabled	Disabled
GPIO3	Group OE, OE_GROUP_9	Normal	Disabled	Enabled
GPIO4	Group OE, OE_GROUP_10	Normal	Disabled	Enabled

Table 1-5 LMK3H2108A01 Input Settings, OTP Page 0

Input	Powered Up/Down	Input Format	Input Termination
IN_0	Powered Down	N/A (IN0 Unused)	None, DC
IN_1	Powered Up	Differential IN1	None, AC
IN_2	Powered Down	N/A (IN2 Unused)	None, DC

Table 1-6 LMK3H2108A01 Output Settings, OTP Page 0

Output	Frequency (MHz)	Format	Clock Source	Output State	OE Group	SSC Behavior
OUT0	100	100 Ω LP-HCSL	PATH1	Enabled	OE_GROUP_9	Disabled
OUT1	100	100 Ω LP-HCSL	PATH1	Enabled	OE_GROUP_10	Disabled
OUT2	100	100 Ω LP-HCSL	PATH1	Enabled	OE_GROUP_10	Disabled
OUT3	100	100 Ω LP-HCSL	PATH1	Enabled	OE_GROUP_10	Disabled
OUT4	100	100 Ω LP-HCSL	PATH1	Enabled	OE_GROUP_10	Disabled
OUT5	100	100 Ω LP-HCSL	PATH1	Enabled	OE_GROUP_7	Disabled
OUT6	100	100 Ω LP-HCSL	PATH1	Enabled	OE_GROUP_7	Disabled
OUT7	100	100 Ω LP-HCSL	PATH1	Disabled	No OE Group	Disabled

Table 1-7 LMK3H2108A01 GPI Settings, OTP Page 1

GPI Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPI0	GPI	Normal	Disabled	Disabled
GPI1	GPI	Normal	Disabled	Disabled
GPI2	GPI	Normal	Disabled	Disabled
GPI3	GPI	Normal	Disabled	Disabled
GPI4	GPI	Normal	Disabled	Disabled
GPI5	GPI	Normal	Disabled	Disabled

Table 1-8 LMK3H2108A01 GPIO Settings, OTP Page 1

GPIO Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPIO0	Dynamic OTP	Normal	Disabled	Disabled
GPIO1	Group OE, OE_GROUP_7	Normal	Disabled	Enabled
GPIO2	Dynamic OTP	Normal	Disabled	Disabled
GPIO3	Group OE, OE_GROUP_9	Normal	Disabled	Enabled
GPIO4	Group OE, OE_GROUP_10	Normal	Disabled	Enabled

Table 1-9 LMK3H2108A01 Input Settings, OTP Page 1

Input	Powered Up/Down	Input Format	Input Termination
IN_0	Powered Down	N/A (IN0 Unused)	None, DC
IN_1	Powered Up	Differential IN1	None, AC
IN_2	Powered Down	N/A (IN2 Unused)	None, DC

Table 1-10 LMK3H2108A01 Output Settings, OTP Page 1

Output	Frequency (MHz)	Format	Clock Source	Output State	OE Group	SSC Behavior
OUT0	100	100 Ω LP-HCSL	IN_1	Enabled	OE_GROUP_9	Disabled
OUT1	100	100 Ω LP-HCSL	IN_1	Enabled	OE_GROUP_10	Disabled
OUT2	100	100 Ω LP-HCSL	IN_1	Enabled	OE_GROUP_10	Disabled
OUT3	100	100 Ω LP-HCSL	IN_1	Enabled	OE_GROUP_10	Disabled
OUT4	100	100 Ω LP-HCSL	IN_1	Enabled	OE_GROUP_10	Disabled
OUT5	100	100 Ω LP-HCSL	IN_1	Enabled	OE_GROUP_7	Disabled
OUT6	100	100 Ω LP-HCSL	IN_1	Enabled	OE_GROUP_7	Disabled
OUT7	100	100 Ω LP-HCSL	IN_1	Disabled	No OE Group	Disabled

Table 1-11 LMK3H2108A01 GPI Settings, OTP Page 2

GPI Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPI0	GPI	Normal	Disabled	Disabled
GPI1	GPI	Normal	Disabled	Disabled
GPI2	GPI	Normal	Disabled	Disabled
GPI3	GPI	Normal	Disabled	Disabled
GPI4	GPI	Normal	Disabled	Disabled
GPI5	GPI	Normal	Disabled	Disabled

Table 1-12 LMK3H2108A01 GPIO Settings, OTP Page 2

GPIO Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPIO0	Dynamic OTP	Normal	Disabled	Disabled
GPIO1	Group OE, OE_GROUP_7	Normal	Disabled	Enabled
GPIO2	Dynamic OTP	Normal	Disabled	Disabled
GPIO3	Group OE, OE_GROUP_9	Normal	Disabled	Enabled
GPIO4	Group OE, OE_GROUP_10	Normal	Disabled	Enabled

Table 1-13 LMK3H2108A01 Input Settings, OTP Page 2

Input	Powered Up/Down	Input Format	Input Termination
IN_0	Powered Down	N/A (IN0 Unused)	None, DC
IN_1	Powered Up	Differential IN1	None, AC
IN_2	Powered Down	N/A (IN2 Unused)	None, DC

Table 1-14 LMK3H2108A01 Output Settings, OTP Page 2

Output	Frequency (MHz)	Format	Clock Source	Output State	OE Group	SSC Behavior
OUT0	100	100 Ω LP-HCSL	PATH1	Enabled	OE_GROUP_9	Disabled
OUT1	100	100 Ω LP-HCSL	PATH0	Enabled	OE_GROUP_10	Enabled, -0.5% Down-spread
OUT2	100	100 Ω LP-HCSL	PATH0	Enabled	OE_GROUP_10	Enabled, -0.5% Down-spread
OUT3	100	100 Ω LP-HCSL	PATH0	Enabled	OE_GROUP_10	Enabled, -0.5% Down-spread
OUT4	100	100 Ω LP-HCSL	PATH0	Enabled	OE_GROUP_10	Enabled, -0.5% Down-spread
OUT5	100	100 Ω LP-HCSL	PATH0	Enabled	OE_GROUP_7	Enabled, -0.5% Down-spread
OUT6	100	100 Ω LP-HCSL	PATH0	Enabled	OE_GROUP_7	Enabled, -0.5% Down-spread
OUT7	100	100 Ω LP-HCSL	PATH0	Disabled	No OE Group	Enabled, -0.5% Down-spread

Table 1-15 LMK3H2108A01 GPI Settings, OTP Page 3

GPI Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPI0	GPI	Normal	Disabled	Disabled
GPI1	GPI	Normal	Disabled	Disabled
GPI2	GPI	Normal	Disabled	Disabled
GPI3	GPI	Normal	Disabled	Disabled
GPI4	GPI	Normal	Disabled	Disabled
GPI5	GPI	Normal	Disabled	Disabled

Table 1-16 LMK3H2108A01 GPIO Settings, OTP Page 3

GPIO Pin	Pin Behavior	Polarity	Internal Pull-Down	Internal Pull-Up
GPIO0	Dynamic OTP	Normal	Disabled	Disabled
GPIO1	Group OE, OE_GROUP_7	Normal	Disabled	Enabled
GPIO2	Dynamic OTP	Normal	Disabled	Disabled
GPIO3	Group OE, OE_GROUP_9	Normal	Disabled	Enabled
GPIO4	Group OE, OE_GROUP_10	Normal	Disabled	Enabled

Table 1-17 LMK3H2108A01 Input Settings, OTP Page 3

Input	Powered Up/Down	Input Format	Input Termination
IN_0	Powered Down	N/A (IN0 Unused)	None, DC
IN_1	Powered Up	Differential IN1	None, AC
IN_2	Powered Down	N/A (IN2 Unused)	None, DC

Table 1-18 LMK3H2108A01 Output Settings, OTP Page 3

Output	Frequency (MHz)	Format	Clock Source	Output State	OE Group	SSC Behavior
OUT0	100	100 Ω LP-HCSL	PATH1	Disabled	OE_GROUP_9	Disabled
OUT1	100	100 Ω LP-HCSL	PATH1	Disabled	OE_GROUP_10	Disabled
OUT2	100	100 Ω LP-HCSL	PATH1	Disabled	OE_GROUP_10	Disabled
OUT3	100	100 Ω LP-HCSL	PATH1	Disabled	OE_GROUP_10	Disabled
OUT4	100	100 Ω LP-HCSL	PATH1	Disabled	OE_GROUP_10	Disabled
OUT5	100	100 Ω LP-HCSL	PATH1	Disabled	OE_GROUP_7	Disabled
OUT6	100	100 Ω LP-HCSL	PATH1	Disabled	OE_GROUP_7	Disabled
OUT7	100	100 Ω LP-HCSL	PATH1	Disabled	No OE Group	Disabled