SLUUDG2 November   2025 LMK3H2108

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Configuration Overview
    1. 1.1 LMK3H2108A0E Configuration Information
  5. 2Revision History

1.1 LMK3H2108A0E Configuration Information

Table 1-1 LMK3H2108A0E Freuqency Configuration
OTP PageOUT0 (MHz)OUT1 (MHz)OUT2 (MHz)OUT3 (MHz)OUT4 (MHz)OUT5 (MHz)OUT6 (MHz)OUT7 (MHz)
OTP Page 000000000
OTP Page 1100100100100100100100100
OTP Page 2100100100100100100100100
OTP Page 3100100100100100100100100
Table 1-2 LMK3H2108A0E I2C Configuration
OTP PageI2C Configuration
OTP Page 0

I2C Address: 0x68

1 Byte Register Addressing

OTP Page 1

I2C Address: 0x68

1 Byte Register Addressing

OTP Page 2

I2C Address: 0x68

1 Byte Register Addressing

OTP Page 3

I2C Address: 0x68

1 Byte Register Addressing

OTP Page 0

Table 1-3 LMK3H2108A0E GPI Settings, OTP Page 0
GPI PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPI0GPIInvertedEnabledDisabled
GPI1GPIInvertedEnabledDisabled
GPI2GPIInvertedEnabledDisabled
GPI3GPIInvertedEnabledDisabled
GPI4GPIInvertedEnabledDisabled
GPI5GPIInvertedEnabledDisabled
Table 1-4 LMK3H2108A0E GPIO Settings, OTP Page 0
GPIO PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPIO0GPIInvertedEnabledDisabled
GPIO1Dynamic OTPNormalEnabledDisabled
GPIO2Dynamic OTPNormalEnabledDisabled
GPIO3Global OEInvertedEnabledDisabled
GPIO4GPIInvertedEnabledDisabled
Table 1-5 LMK3H2108A0E Input Settings, OTP Page 0
InputPowered Up/DownInput FormatInput Termination
IN_0Powered UpDifferential IN0None, DC
IN_1Powered DownN/A (IN1 Unused)None, DC
IN_2Powered UpDifferential IN2None, DC
Table 1-6 LMK3H2108A0E Output Settings, OTP Page 0
OutputFrequency (MHz)FormatClock SourceOutput StateOE GroupSSC Behavior
OUT0085 Ω LP-HCSLIN_0EnabledGlobal OE OnlyDisabled
OUT1085 Ω LP-HCSLIN_2EnabledGlobal OE OnlyDisabled
OUT2085 Ω LP-HCSLIN_2EnabledGlobal OE OnlyDisabled
OUT3085 Ω LP-HCSLIN_2EnabledGlobal OE OnlyDisabled
OUT4085 Ω LP-HCSLIN_2EnabledGlobal OE OnlyDisabled
OUT5085 Ω LP-HCSLIN_0EnabledGlobal OE OnlyDisabled
OUT6085 Ω LP-HCSLIN_0EnabledGlobal OE OnlyDisabled
OUT7085 Ω LP-HCSLIN_0EnabledGlobal OE OnlyDisabled

OTP Page 1

Table 1-7 LMK3H2108A0E GPI Settings, OTP Page 1
GPI PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPI0GPIInvertedEnabledDisabled
GPI1GPIInvertedEnabledDisabled
GPI2GPIInvertedEnabledDisabled
GPI3GPIInvertedEnabledDisabled
GPI4GPIInvertedEnabledDisabled
GPI5GPIInvertedEnabledDisabled
Table 1-8 LMK3H2108A0E GPIO Settings, OTP Page 1
GPIO PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPIO0GPIInvertedEnabledDisabled
GPIO1Dynamic OTPNormalEnabledDisabled
GPIO2Dynamic OTPNormalEnabledDisabled
GPIO3Global OEInvertedEnabledDisabled
GPIO4GPIInvertedEnabledDisabled
Table 1-9 LMK3H2108A0E Input Settings, OTP Page 1
InputPowered Up/DownInput FormatInput Termination
IN_0Powered DownDifferential IN0None, DC
IN_1Powered DownN/A (IN1 Unused)None, DC
IN_2Powered DownDifferential IN2None, DC
Table 1-10 LMK3H2108A0E Output Settings, OTP Page 1
OutputFrequency (MHz)FormatClock SourceOutput StateOE GroupSSC Behavior
OUT010085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyDisabled
OUT110085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyDisabled
OUT210085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyDisabled
OUT310085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyDisabled
OUT410085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyDisabled
OUT510085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyDisabled
OUT610085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyDisabled
OUT710085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyDisabled

OTP Page 2

Table 1-11 LMK3H2108A0E GPI Settings, OTP Page 2
GPI PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPI0GPIInvertedEnabledDisabled
GPI1GPIInvertedEnabledDisabled
GPI2GPIInvertedEnabledDisabled
GPI3GPIInvertedEnabledDisabled
GPI4GPIInvertedEnabledDisabled
GPI5GPIInvertedEnabledDisabled
Table 1-12 LMK3H2108A0E GPIO Settings, OTP Page 2
GPIO PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPIO0GPIInvertedEnabledDisabled
GPIO1Dynamic OTPNormalEnabledDisabled
GPIO2Dynamic OTPNormalEnabledDisabled
GPIO3Global OEInvertedEnabledDisabled
GPIO4GPIInvertedEnabledDisabled
Table 1-13 LMK3H2108A0E Input Settings, OTP Page 2
InputPowered Up/DownInput FormatInput Termination
IN_0Powered DownDifferential IN0None, DC
IN_1Powered DownN/A (IN1 Unused)None, DC
IN_2Powered DownDifferential IN2None, DC
Table 1-14 LMK3H2108A0E Output Settings, OTP Page 2
OutputFrequency (MHz)FormatClock SourceOutput StateOE GroupSSC Behavior
OUT010085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.25% Down-spread
OUT110085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.25% Down-spread
OUT210085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.25% Down-spread
OUT310085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.25% Down-spread
OUT410085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.25% Down-spread
OUT510085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.25% Down-spread
OUT610085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.25% Down-spread
OUT710085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.25% Down-spread

OTP Page 3

Table 1-15 LMK3H2108A0E GPI Settings, OTP Page 3
GPI PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPI0GPIInvertedEnabledDisabled
GPI1GPIInvertedEnabledDisabled
GPI2GPIInvertedEnabledDisabled
GPI3GPIInvertedEnabledDisabled
GPI4GPIInvertedEnabledDisabled
GPI5GPIInvertedEnabledDisabled
Table 1-16 LMK3H2108A0E GPIO Settings, OTP Page 3
GPIO PinPin BehaviorPolarityInternal Pull-DownInternal Pull-Up
GPIO0GPIInvertedEnabledDisabled
GPIO1Dynamic OTPNormalEnabledDisabled
GPIO2Dynamic OTPNormalEnabledDisabled
GPIO3Global OEInvertedEnabledDisabled
GPIO4GPIInvertedEnabledDisabled
Table 1-17 LMK3H2108A0E Input Settings, OTP Page 3
InputPowered Up/DownInput FormatInput Termination
IN_0Powered DownDifferential IN0None, DC
IN_1Powered DownN/A (IN1 Unused)None, DC
IN_2Powered DownDifferential IN2None, DC
Table 1-18 LMK3H2108A0E Output Settings, OTP Page 3
OutputFrequency (MHz)FormatClock SourceOutput StateOE GroupSSC Behavior
OUT010085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.5% Down-spread
OUT110085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.5% Down-spread
OUT210085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.5% Down-spread
OUT310085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.5% Down-spread
OUT410085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.5% Down-spread
OUT510085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.5% Down-spread
OUT610085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.5% Down-spread
OUT710085 Ω LP-HCSLPATH1EnabledGlobal OE OnlyEnabled, -0.5% Down-spread