AFE8092 0.9-V, 1.2-V, and 1.8-V groups are powered directly from DC-DC as shown in Figure 2-9. All DC-DC have additional second stage LC filtering using ferrite bead and filter caps. Additionally, each group of power rail is isolated with additional ferrite bead filtering to suppress high frequency noise from either side. Additional ferrite bead filtering with AFE decoupling capacitor should be designed without causing supply ringing during load step and meet settling time as close as DC-DC output response as mentioned in AFE80xx Supply Settling (Section 2.2). See Section 4.1.4 of TIDA-01579 for ferrite bead filter design with damping resistor. Optimized ferrite LC bead filtering can eliminate cross channel carrier coupling and prevent inter-modulation spurious in RF spectrum.

In Figure 2-9 power design, 1.8-V PLL rail can be powered from dedicated TPS62913 DC-DC power supply to avoid coupling of loads transient ripple from 1.8-V supply into 1.8-V PLL bandwidth of AFE8092 when used for TDD Wireless systems.

For Multichannel AFE architecture a single DC-DC TPS62913 can be used to power up multiple 1.8-V PLL supply rails. 0.9-V and 1.2-V rails of Multichannel AFE architecture (64T64R) can be powered from single or dual TPS543B20 high current synchronous converter.

All DC-DC is externally synced with 1-MHz switching clock to eliminate any Beating spurious in RF spectrum. Additional phase shift in clock signal can be added to reduce input ripple current of DC-DC blocks. A low-cost clock sync circuit is proposed as shown in Figure 2-10 using square pulse oscillator using TLV3501 and D flip flop, NAND Gate to generate 90° phase shifted clock pulses.