SLVAFQ2 December   2023 TPS65219

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Power Delivery Networks (PDNs)
    1. 2.1 TPS652190C Power Rails Configuration
    2. 2.2 LP87334F Power Rails Configuration
    3. 2.3 Powering i.MX 8M Plus and DDR4
    4. 2.4 Powering i.MX 8M Plus and LDDR4
    5. 2.5 PMICs Digital Configuration
    6. 2.6 Power-Up Sequence
    7. 2.7 Power-Down Sequence
  6. 3Supporting i.MX 8M Plus Low Power Modes
  7. 4PMIC Schematic Example
  8. 5TPS6521905 User-Programmable Version
  9. 6Summary
  10. 7References

2.6 Power-Up Sequence

This section shows the power-up sequence. The primary TPS65219 PMIC uses the GPIOs to enable the secondary PMIC and external discrete components.

GUID-20231011-SS0I-VQMV-LHW9-L67QGXGBMSV9-low.svg Figure 2-3 Power-Up Sequence