SLVAFQ2 December   2023 TPS65219

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Power Delivery Networks (PDNs)
    1. 2.1 TPS652190C Power Rails Configuration
    2. 2.2 LP87334F Power Rails Configuration
    3. 2.3 Powering i.MX 8M Plus and DDR4
    4. 2.4 Powering i.MX 8M Plus and LDDR4
    5. 2.5 PMICs Digital Configuration
    6. 2.6 Power-Up Sequence
    7. 2.7 Power-Down Sequence
  6. 3Supporting i.MX 8M Plus Low Power Modes
  7. 4PMIC Schematic Example
  8. 5TPS6521905 User-Programmable Version
  9. 6Summary
  10. 7References

1 Introduction

This application note provides a reference power design for the i.MX 8M Plus processor, as well as memory and external peripherals in the system. Powering this type of processor demands requirements such as sufficient current headroom, tight transient requirements, and a number of rails that can be fully controlled for power up and power down sequencing. The TPS65219 is a cost and space optimized design developed by Texas Instruments. This Power Management IC (PMIC) has flexible analog and digital resources that can be configured to supply a variety of processors and SoCs with different power requirements. Factory programmed orderable part numbers (OPNs) come with default non-Volatile Memory (NVM) settings to support specific use cases. Alternatively, the TPS65219 PMIC has a user programmable version that comes with all rails disabled by default and allows customers to program a custom NVM settings for specific output voltages, sequence, etc. When needed, the TPS65219 PMIC can be combined with other PMIC for a multi PMIC design or with external discrete ICs. The TPS65219 GPIOs can be configured to control the enable/disable of external ICs that are part of the power design.

The i.MX 8M Plus™ processor requires a power design that can supply the following main domains: VDD_ARM (for Quad-A53), VDD_SOC (for SoC logic, DRAM controller, GPU, and VPU controllers), NVCC_3V3 (for 3.3V IO), NVCC_1V8 (for 1.8 V IO), NVCC_DRAM (DRAM IO), VDDA (1.8 V analog) and NVCC_SNVS (1.8 V for SNVS/RTC IO). Depending on the application requirements, there might be additional supplies needed, for example NVCC_SD2 (supply for SDHC2 interface). This application note describes a multi-PMIC design using TPS65219+LP8733 PMICs to power i.MX 8M Plus and DDR4. For LPDDR4, TPS65219 is combined with a discrete Buck.

Note: The end user is responsible for validating the NVM settings for proper system use including any safety impact. This document does not provide information about the electrical characteristics, or the functionality of the device. For this information and the full register map, refer to the corresponding device data sheet. In the event of any inconsistency between any user's guide, application note, or other referenced material, the data sheet specification is the definitive source.