3 Design Considerations and Results

Phased shifted dual active bridge converters have good efficiency as long as switches are operating in soft switching. This is difficult to achieve when secondary side voltage is changing, such as a sinus on the AC-side. In TIDA-010954, two methods for phase shift control have been implemented. The control method is explained in following IEEE paper. For heavy power, “Mode II” is implemented around the AC-peak. For light power (AC-slopes & 0-cross of AC signal), “Mode III” has been used. The differences in phase shift control of Mode II and III can be seen in Figure 3-1.

Figure 3-1 Phase Shift Modes and Control Variables

The control variables D₁ and D₂ are used to control power flow and are calculated in the microcontroller (TMS320F28P550), depending on which mode the converter is operating in. It is important to point out that in Mode II the primary voltage V_P is always leading secondary voltage V_S for positive power transfer. For reverse power transfer V_P is always lagging V_S. This is needed to keep the converter in soft switching for heavy power transfer. In Mode III, the primary voltage pulse V_P is fully included inside the second voltage pulse V_S. This is needed to reduce RMS-currents in the transformer and to reduce conduction losses in the switches. In addition to the phase shift control, a frequency control has been implemented to keep the RMS current in the transformer small while the converter is operated in light load. The operating frequency of the converter is varying between 300kHz and 600kHz.

The extended phase shift control with variable frequency modulation runs in a 20kHz (50us) interrupt service routine on the TMS320F28P550 core (150MHz clock speed) and requires less than 40% MCU utilization. This allows to add additional housekeeping routines and run control on a single MCU. Such a low utilization is only possible because the micro controller has advanced features like "configurable logic block (CLB)" to run time critical code in hardware instead of loading the MCU. Additionally, the TMS320P550 has very good peripherals that allow to update PWM in very short time simultaneously for phase shift and frequency modulation. To achieve this on traditional MCUs often an additional FPGA or an ASIC implementation was needed to perform such combined control algorithms.

Using PLEXIM simulator, the design has been simulated to predict proper functionality of the control before HW has been built.

Figure 3-2 shows simulation results for a 40V_DC input and a 230V_AC output under two different load conditions (300W and 600W).

Figure 3-2 Simulation Results for 300W and 600W Load Condition

In the simulation, the mode changes can be seen as little spikes on the current waveform (in red) when the converter changes the mode operation.

The TIDA-010954 has been fabricated on a standard 6-layer PCB. All GaN devices are bottom side cooled and dissipate the power into the PCB without the need for an additional heat sink. Figure 3-3 shows a picture of the converter. The design has a power density of approximately 600W/L. This is about 2x higher than commercial two stage micro inverters available with same power rating today.

Figure 3-3 Photography of Cycloconverter TIDA-010954

The converter was measured under various load conditions in the lab. Figure 3-4 shows the time domain measurements on the AC-output of the converter.

Figure 3-4 Measurement Results for 300W and 600W Load Condition

An excellent match between simulation and measurement is shown inFigure 3-2). The total harmonic distortion measured for full load condition of 600W is only 2.6% and is well below 3% requirement for grid connected micro inverters.

The test under different load conditions is an important performance parameter. The converter needs to achieve high efficiency in full load as well as 50% condition, but also at lighter load. The measured efficiency curve is given in Figure 3-5. The peak efficiency is around 97%.

Figure 3-5 Measurement Efficiency Versus Load Condition

To compare different micro inverter designs, a weighted efficiency has been defined. The most common definitions are Euro and CEC Efficiency. The above curve represents η_EURO approximately 95.4% and η_CEC of approximately 96.4%. This is very high compared to solutions available in the market that are based on traditional two stage topologies.