SLVK158 November   2023 TPS7H6003-SP

PRODUCTION DATA  

  1.   1
  2.   TPS7H6003-SP Single-Event Effects (SEE)
  3.   Trademarks
  4. Introduction
  5. Single-Event Effects (SEE)
  6. Device and Test Board Information
  7. Irradiation Facility and Setup
  8. Depth, Range, and LETEFF Calculation
  9. Test Setup and Procedures
  10. Destructive Single-Event Effects (DSEE)
    1. 7.1 Single-Event Latch-up (SEL) Results
    2. 7.2 Single-Event Burnout (SEB) and Single-Event Gate Rupture (SEGR) Results
  11. Single-Event Transients (SET)
  12. Event Rate Calculations
  13. 10Summary
  14.   A References

Device and Test Board Information

The TPS7H6003-SP is packaged in a 48-pin ceramic package as shown in Figure 3-1. A TPS7H6003-SP evaluation board made specifically for radiation testing was used to evaluate the performance and characteristics of the TPS7H6003-SP under heavy ion radiation. The TPS7H6003-SP evaluation board is shown in Figure 3-2. The board schematic is shown in Figure 3-3.

The package was delidded to reveal the die face for all heavy-ion testing.

GUID-20230922-SS0I-3GVM-X2GV-6S3JMJDQJ5DR-low.svgFigure 3-1 Photograph of Delidded TPS7H6003-SP [Left] and Pinout Diagram [Right]
GUID-20230922-SS0I-GLBN-JGBH-R2LH57JG4NGN-low.jpg Figure 3-2 TPS7H6003-SP EVM Top View

Although not shown here, there are 1-nF capacitors on the HO and LO outputs. See the block diagram for the setup of the capacitive load.

GUID-20230925-SS0I-ZFF0-N0HF-X4SWZLTPPLX0-low.svgFigure 3-3 TPS7H6003-SP Evaluation Board Schematics