SLVUCA5 June   2022

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Before You Begin
  4. 2TPS7B4255EVM-062 Schematic
  5. 3Setup
    1. 3.1 LDO Input/Output Connector Descriptions
      1. 3.1.1 VIN and GND
      2. 3.1.2 VOUT and GND
      3. 3.1.3 EN
    2. 3.2 Optional Load Transient Input/Output Connector Descriptions
      1. 3.2.1 VDD and GND
      2. 3.2.2 J15
      3. 3.2.3 J18
      4. 3.2.4 J19
      5. 3.2.5 J21
      6. 3.2.6 J22
      7. 3.2.7 J23
      8. 3.2.8 J26
      9. 3.2.9 TP3
    3. 3.3 TPS7B4255-Q1 LDO Operation and Component Selection
    4. 3.4 Optional Load Transient Circuit Operation
  6. 4Board Layout
  7. 5Bill of Materials

3.4 Optional Load Transient Circuit Operation

The TPS7B4255EVM-062 evaluation module contains an optional high-performance load transient circuit to allow efficient testing of the TPS7B4255-Q1 LDO load transient performance. To use the optional load transient circuit, install the correct components in accordance with the application. Modify the input and output capacitance connected to the TPS7B4255-Q1 LDO to match the expected operating conditions. Determine the desired peak current to test and modify the parallel resistor combination of R9, R10, R11, R12, and R13 as shown:

Equation 1. I P e a k = V O U T R 9 R 10 R 11 R 12 R 13 + I D C

The slew rate of the load step can be adjusted by C14, R14, R15, and R16. In this section, only R15 and R16 are adjusted to set the slew rate. For a 0-mA to 70-mA to 0-mA load step, use Table 3-1 to select a value of R15 and R16 that results in the desired rise or fall time.

Table 3-1 Suggested Ramp Rate Resistor Values
R15 R16 Rise, Fall Time
3.4 kΩ 2.1 kΩ 700 ns
1.69 kΩ 1.1 kΩ 350 ns
604 Ω 383 Ω 140 ns
332 Ω 169 Ω 70 ns
121 Ω 69.8 Ω 35 ns
37.4 Ω 0 Ω 14 ns

After the EVM is modified (if needed), connect a power supply to banana connectors J20 (VDD) and J25 (GND) with a 5-V DC supply and a 1-A DC current limit. As illustrated in Figure 3-3 and Figure 3-4, the TPS7B4255-Q1 transient response is very fast and the output voltage recovers in well under 1 ms after the initial load transient. Use a pulse-duration limit of 1 ms to prevent excessive heating of the pulsed resistors (R9, R10, R11, R12, and R13). Configure a function generator for the 50-Ω output, in a 0-V DC to 5-V DC square pulse. If necessary, burst mode can be configured in the function generator for repetitive, low duty cycle, load transient testing.

Use J14 to short R7 to GND and configure VOUT to be 5-V DC. A 487-Ω resistor is installed on the EVM at R15, and a 442-Ω resistor is installed on the EVM at R16. These resistors provide approximately 0.5-A/μs slew rate from both 0 mA to 70 mA and 70 mA to 0 mA. Figure 3-3 and Figure 3-4 provide example test data with R15 = 487 Ω and R16 = 442 Ω. The yellow trace is the input voltage, the red trace is the output voltage, and the blue trace is the output current. R9, R10, R11, R12, and R13 provide 70 mA of pulsed load. The resulting test data shows a 50-μA to 70-mA load step on VOUT of the LDO, with only a 1-μF capacitor on the output of the LDO.

Figure 3-3 TPS7B4255EVM-062 Load Transient Results: 50-μA to 70-mA Load Step
Figure 3-4 TPS7B4255EVM-062 Load Transient Results: 70-mA to 50-μA Load Step