SLVUCI4B february   2023  – may 2023 TPS7H5001-SP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2System Design Theory
    1. 2.1  Switching Frequency
    2. 2.2  Leading Edge Blanking
    3. 2.3  Dead Time
    4. 2.4  Enable and UVLO
    5. 2.5  Output Voltage Programing
    6. 2.6  Soft Start
    7. 2.7  Sensing Circuit
    8. 2.8  FAULT Mode
    9. 2.9  HICCUP Mode
    10. 2.10 Slope Compensation
    11. 2.11 Output Capacitance
    12. 2.12 Compensation
  6. 3Test Results
  7. 4Bill of Materials
  8. 5Schematics
  9. 6PCB Layouts
  10. 7References
  11. 8Revision History

PCB Layouts

Figure 6-1 through Figure 6-13 show the EVM PCB layout images.


GUID-20221215-SS0I-MBWL-FCKG-5RLQ4KRB1Z7P-low.gif

Figure 6-1 Top Overlay

GUID-20221215-SS0I-W637-03CD-LJSZHFW2KNN0-low.gif

Figure 6-3 Top Layer

GUID-20221215-SS0I-LTFB-H1W8-TGPZNX580LTN-low.gif

Figure 6-5 Signal Layer 2

GUID-20221215-SS0I-KKPK-GXNK-6JVMX8LCJW2R-low.gif

Figure 6-7 Signal Layer 4
GUID-20221215-SS0I-MDCH-HW49-H3RWZNMFPKLK-low.gifFigure 6-9 Signal Layer 6
GUID-20221215-SS0I-GHWG-RSFC-TPFMZ4WKKQGT-low.gifFigure 6-11 Bottom Solder Mask
GUID-20221215-SS0I-0PPM-MNZ5-3WVNGRZMSBWP-low.gifFigure 6-13 Drill Drawing

GUID-20221215-SS0I-XNNN-JLRB-NX7RCFDXCXFJ-low.gif

Figure 6-2 Top Solder

GUID-20221215-SS0I-BDFL-T6NM-KHZSTFJLFMPL-low.gif

Figure 6-4 Signal Layer 1

GUID-20221215-SS0I-BJGD-RWML-LC11TLXTBZJD-low.gif

Figure 6-6 Signal Layer 3

GUID-20221215-SS0I-WQQK-JXJC-F7QNWWWXTH0L-low.gif

Figure 6-8 Signal Layer 5
GUID-20221215-SS0I-PSCF-Z8QB-LQXJGWGBJXBG-low.gifFigure 6-10 Bottom Solder
GUID-20221215-SS0I-RKFK-VKTD-ZPWHMVZWMWSG-low.gifFigure 6-12 Bottom Overlay