SLVUD30A December   2024  – December 2025 TPS65214

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2PDN and Sequence Diagrams
    1. 2.1 TPS6521401 Power Sequence and Example Block Diagram
  6. 3NVM Device Settings
    1. 3.1  Device ID
    2. 3.2  Enable Settings
    3. 3.3  Regulator Voltage Settings
    4. 3.4  Sequence Settings
      1. 3.4.1 Power-Up Sequence
      2. 3.4.2 Power-Down Sequence
    5. 3.5  EN / PB / VSENSE Settings
    6. 3.6  Multi-Function Pin Settings
    7. 3.7  Over-Current Deglitch
    8. 3.8  Mask Settings
    9. 3.9  Discharge Check
    10. 3.10 Low Power Mode
  7. 4Revision History

3.5 EN / PB / VSENSE Settings

The EN/PB/VSENSE pin is used to enable or disable the PMIC. This pin can be configured in one of three ways: EN, PB or VSENSE. The table below shows the default configuration for this pin. Please note, if the FSD (First supply detection) feature is enabled, the device goes from "No Power" to "Active" state, executing the power-up sequence as soon as the voltage on VSYS is above the POR threshold. In this scenario, the EN/PB/VSENSE pin is ignored ONLY during the first power-up.

Table 3-10 EN / PB / VSENSE Settings
Register AddressField NameValueDescription
Pin Config0x20EN_PB_VSENSE_CONFIG0x1Device Enable Configuration
ON Deglitch0x20EN_PB_VSENSE_DEGL0x0short (typ: 120us for EN/VSENSE and 200ms for PB)
First Supply Detection0x20PU_ON_FSD0x0First Supply Detection (FSD) Not enabled.
Note: The deglitch configured on register field "EN_PB_VSENSE_DEGL" is for the ON request. The deglitch for the OFF request is not configurable. The parameters that are not configurable can be found in the Specifications section of the device data sheet.