5 Solving for C

To further improve the narrowband width match (in other words, make it narrower), add the last component in the RCL reactive match from Figure 2. Placing the C term in parallel with the inductor creating an LC tank. It seems counterintuitive to add capacitance back into the front-end match after placing the 18nH inductor to combat the ADC’s internal capacitance, but it tightens the filter match. In order to solve for a parallel C value to complete the LC tank, use Equation 7:

Solving for C = 1.6pF.

Let’s put this value (1.6pF capacitor or nearest standard value) in the front-end design and rerun the passband BW sweep; see Figure 9.

As can be seen, adding in the additional 1.5pF capacitor in parallel with the 18nH inductor, creating that LC tank, doesn’t really improve or narrow the match (see mini-dashed curve).

The LC tank method will work, but with a few considerations. Removing the internal C by solving the external L value (18nH) will help but may not entirely prove to be the end solution. To implement this accurately, you need to use a much larger C value to completely remove any internal and residual external C parasitics. You are competing with balun and trace parasitics, as well as the ADC’s internal sampling capacitor, which is dynamic in nature as the sample switch opens and closes quickly.

Let’s choose a higher value for C, such as 9.1pF, re-solve for L in using Equation 7 again:

Solving for L = 3nH.

With these values in place of the front-end design, Figure 10 shows the results after re-running the passband BW sweep.

As you can see, there is a considerable improvement when narrowing the bandwidth match to 350MHz wide (the thick dashed curve) by increasing the external C in order to further improve the NB match response. Typically, it’s good to use at least twice the value of C based on the aggregate ADC’s internal sampling network as a good starting point. Adding this term externally will only further improve RL in the band of choice.

You can then adjust the L value, the C value, or both to help widen or narrow or shift the BW needed to match for your application needs. You will need to remember these values for the layout, balun and ADC input model; it is not possible to simulate all parasitic nuances, and some empirical experience might be necessary in order to gauge the match properly.

Figure 11 illustrates the signal-to-noise ratio (SNR) and second- and third-order harmonics (HD2 and HD3) collected over the NB application example to further verify the ADC’s performance within the 940MHz band.

An analog input center frequency of 940MHz is a bit outside the ADC datasheet measurement specification. The collected values do follow the correct trend for all the collected measurements, SNR, HD2 and HD3, however, and degradation will continue to occur as the input RL degrades >940MHz for this particular ADC.