1 Introduction

Block diagram of the LMX1205 outputs is shown in Figure 1-1. Consider a case, where LMX1205 is used as buffer/multiplier/divider in the clock path (CH0-CH3) and is required that all the channels (CH0-CH3) and sysref (SYS0-SYS3) need to be in sync and deterministic irrespective of the power supply toggling. This application note covers the steps to be followed to get that deterministic nature with lab measured waveforms using LMX1205 tics-pro. In general, sysref channels are low frequency clocks(<200MHz). Sync Signal is an external signal which can be both AC coupled and DC coupled. By default, it is AC coupled in LMX1205.

Figure 1-1 Sync Signal Driving Two LMX1205

There are different modes of operation to be taken care before we see the final synced output, which is discussed in the subsequent sections. Assuming (as shown in Figure 1-2) somehow the Sync Signal rise edge is coming on the clock negative edge. After some delay, SYS0 and SYS4 are synced and deterministic. Absolute delay depends on the divider used for sysref path. But for a particular sysref divider settings, no matter how many power cycles done, it is always deterministic. This application note focus on using sysref outputs for explaining the concepts and same is applicable for other channel outputs also. If sync signal is not going from low to high in one input clock window to two LMX1205s, then determinism is not achievable.

Figure 1-2 Pre and Post Sync Waveform Illustration