SNLU325 October   2023 DP83867CR , DP83867CS , DP83867E , DP83867IR , DP83867IS

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Access Methods
    1. 1.1 Register Programming Through SMBus
    2. 1.2 Device Configuration Through External EEPROM
  5. 2Register Mapping
    1. 2.1 Share Registers
    2. 2.2 Channel Registers
  6. 3Equalization Control Settings
  7. 4CTLE Index and Flat Gain Selection Matrix
  8. 5Programming Examples
  9. 6References
  10. 7Revision History

2.1 Share Registers

Table 2-1 General Register (Offset = 0xE2) [reset = 0x0]
BitFieldTypeResetDescription
7RESERVEDR0x0Reserved
6rst_i2c_regsR/W/SC0x0Device Reset Control: Reset all I2C registers to default values (self- clearing).
5RESERVEDR0x0Reserved
4RESERVEDR0x0Reserved
3RESERVEDR0x0Reserved
2RESERVEDR0x0Reserved
1RESERVEDR0x0Reserved
0frc_eeprm_rdR/W/SC0x0Override MODE and READ_EN_N status to force manual EEPROM Configuration Load.
Table 2-2 DEVICE_ID0 Register (Offset = 0xF0) [reset = 0x02]
BitFieldTypeResetDescription
7:4RESERVEDR0x0Reserved
3device_id0_3R0x0Device ID0 [3:1]: 011
2device_id0_2R0x0see MSB
1device_id0_1R0x1see MSB
0RESERVEDRXReserved
Table 2-3 DEVICE_ID1 Register (Offset = 0xF1) [reset = 0x29]
BitFieldTypeResetDescription
7device_id[7]R0x0Device ID 0010 1001: DS320PR410
6device_id[6]R0x0see MSB
5device_id[5]R0x1see MSB
4device_id[4]R0x0see MSB
3device_id[3]R0x1see MSB
2device_id[2]R0x0see MSB
1device_id[1]R0x0see MSB
0device_id[0]R0x1see MSB