SNVA869 November   2020 LP875761-Q1

 

  1.   Trademarks
  2. 1Design Parameters
  3. 2Power Solution
  4. 3Schematic
  5. 4Layout
    1. 4.1 Layout Considerations
    2. 4.2 Example Layout
  6. 5Recommended External Components
  7. 6Measurements
  8. 7Conclusion
  9. 8References

2 Power Solution

Figure 2-1 shows an example block diagram of LP875761-Q1 device powering the EyeQ4 High core rail, and LP87563x PMIC powering the other required rails. PMIC from the LP87563x family could be configured to power the other rails depending on use case.

GUID-3E5BC4F3-20B6-46A2-8457-E0532BF0820E-low.gif Figure 2-1 EyeQ4 High Power Solution Block Diagram

After the devices are powered, the microcontroller can set the EN pin high to enable the PMIC. Startup delay of the LP875761ARNFRQ1 has been set to 0 ms. Full OTP register settings of LP875761ARNFRQ1 can be found in LP875761A-Q1 Technical Reference Manual. I2C can be used to read status registers and reset interrupts.