SNVU753A November   2019  – May 2021 TPS542A52

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Before You Begin
  3. 2Description
    1. 2.1 Typical End-User Applications
    2. 2.2 EVM Features
    3. 2.3 TPS542A52EVM-059 PCB
  4. 3TPS542A52EVM-059 Bottom Circuit
    1. 3.1 Modifications
      1. 3.1.1 Output Voltage Setpoint
      2. 3.1.2 Enable and Undervoltage Lockout
      3. 3.1.3 External Clock Synchronization
      4. 3.1.4 Load Step with Function Generator
    2. 3.2 Bottom Circuit Schematic
    3. 3.3 Test Setup and Results
      1. 3.3.1  Input/Output Connections
      2. 3.3.2  Start Up Procedure
      3. 3.3.3  Electrical Performance Specifications and Results
      4. 3.3.4  Efficiency
      5. 3.3.5  Power Loss
      6. 3.3.6  Load Regulation
      7. 3.3.7  Transient Response
      8. 3.3.8  Loop Response
      9. 3.3.9  Output Voltage Ripple
      10. 3.3.10 Thermal Data
  5. 4TPS542A52EVM-059 Top Circuit (Small Layout Area Design)
    1. 4.1 Modifications
      1. 4.1.1 Output Voltage Setpoint
      2. 4.1.2 Enable and Undervoltage Lockout
      3. 4.1.3 External Clock Synchronization
      4. 4.1.4 Load Step with Function Generator
    2. 4.2 TPS542A52EVM-059 Top Circuit (Small Layout Area) Schematic
    3. 4.3 Test Setup and Results
      1. 4.3.1  Input/Output Connections
      2. 4.3.2  Start Up Procedure
      3. 4.3.3  Electrical Performance Specifications and Results
      4. 4.3.4  Efficiency
      5. 4.3.5  Power Loss
      6. 4.3.6  Load Regulation
      7. 4.3.7  Line Regulation
      8. 4.3.8  Transient Response
      9. 4.3.9  Loop Response
      10. 4.3.10 Output Voltage Ripple
      11. 4.3.11 Start Up
  6. 5TPS542A52EVM-059 PCB Layout
  7. 6List of Materials
  8. 7Revision History

4.1.2 Enable and Undervoltage Lockout

The operation of the TPS542A52 can be enabled or disabled using J3_2. The EN pin of the TPS542A52 is connected to J3_2-2 (pin 2 of J3_2) and TP14_2. The EN pin threshold is 1.2 V. By leaving J3_2-2 floating, a pullup current source internal to the TPS542A52 enables the device, and the device is operational across all valid input voltages (4 V - 18 V).

Undervoltage lockout (UVLO) can be implemented by connecting a jumper between J3_2-2 and J3_2-3. In this configuration, R12_2 and R15_2 should be populated according to the TPS542A52 device data sheet based on the desired UVLO requirements. By default, R12_2 and R15_2 are not populated.

The TPS542A52 can be disabled by pulling J3_2-2 (the EN pin) below 1.2 V. When J3_2-2 is brought below 1.2 V, the regulator stop switching and enters into a low power shutdown mode.

To externally control the EN pin of the TPS542A52, a control signal referenced to AGND (TP15_2, TP16_2, or TP17_2, recommended between 0 V and 5.5 V) can be connected directly to the EN_2 test point (TP14_2). Using this method, a jumper on J3_2 is not necessary.

The converter can be put into shutdown mode manually by connecting a jumper between J3_2-2 and J3_2-1, which grounds the EN pin.

Default setting: J3_2 open, EN floating for always-on operation.

Table 4-1 Enable Pin Selection
J3_2 CONNECTIONENABLE SELECTION
J3_2-2 floatingDevice is enabled
J3_2-2 and J3_2-3 shortedUVLO implemented if R12_2 and R15_2 are populated - see data sheet for details
J3_2-1 and J3_2-2 shortedConverter is disabled