SPRACC0A November   2017  – November 2020 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377D-EP , TMS320F28377D-Q1 , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379D-Q1

 

  1.   Trademarks
  2. Introduction and Scope
  3. SRAM Bit Array
  4. Sources of SRAM Failures
    1. 3.1 Manufacturing Defects
      1. 3.1.1 Time Zero Fails
      2. 3.1.2 Latent Fails
    2. 3.2 Circuit Drift With Usage
    3. 3.3 Circuit Overstress
    4. 3.4 Soft Errors
      1. 3.4.1 Radioactive Events
      2. 3.4.2 Dynamic Voltage Events
      3. 3.4.3 Summary of Error Sources
  5. Methods for Managing Memory Failures in Electronic Systems
    1. 4.1 Start-Up Testing
    2. 4.2 In-System Testing
    3. 4.3 Parity Detection
    4. 4.4 Error Detection and Correction (EDAC)
    5. 4.5 Redundancy
  6. Comparisons and Conclusions
  7. C2000 Memory Types Example
    1. 6.1 TMS320F2837xD
  8. Memory Types
    1. 7.1 Dedicated RAM (Mx and Dx RAM)
    2. 7.2 Local Shared RAM (LSx RAM)
    3. 7.3 Global Shared RAM (GSx RAM)
    4. 7.4 CPU Message RAM (CPU MSGRAM)
    5. 7.5 CLA Message RAM (CLA MSGRAM)
  9. Summary
  10. References
  11. 10Revision History

Dynamic Voltage Events

Any electronic circuitry that involves switching will have dynamic voltage events, even on an integrated circuit there are voltage events. For example, any time the main system clock switches, many other transistors transition and there is some noise on the power plane. While the voltage events within the semiconductor device are small, a marginal bit cell might be disturbed if it happens during a read or write to the bit cell. However, the devices are tested with enough margins to screen out such bit cells so this is not a concern at the system level. Voltage events that are large enough to disturb a margined bit cell come from off chip or operating the devices out of data sheet specification. Even so, it will happen only to the weaker bits (weaker due to normal and expected process variation). Therefore, single bit detection is adequate to address such events.

Multi-bit read or write failures can happen due to a significant dynamic voltage event. This is indicative of a voltage issue and best addressed with voltage monitoring rather than memory monitoring.