SPRACK2A September   2019  – March 2020 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1

 

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3.1.7 Diagnostic Features (PBIST/HWBIST)

F28004x documents refer to PBIST as the controller that executes configurable memory tests routines as part of the boot up sequence. In F28002x documents and in future C2000 device documents, this module is referred to as MPOST (memory power on self-test). PBIST (MPOST) is enabled as part of the boot up sequence in both F28004x and F28002x devices. HWBIST is a self-test controller for the CPU for fault coverage in safety applications. HWBIST can be invoked from user application code. HWBIST is available only in the F28002x device.