SPRADO9 March   2025 AM62L

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Processor Core and Compute Benchmarks
    1. 2.1 Dhrystone
    2. 2.2 Whetstone
    3. 2.3 Linpack
    4. 2.4 NBench
    5. 2.5 CoreMark-Pro
    6. 2.6 Fast Fourier Transform
    7. 2.7 Cryptographic Benchmarks
  6. 3Memory System Benchmarks
    1. 3.1 Memory Bandwidth and Latency
      1. 3.1.1 LMBench
      2. 3.1.2 STREAM
    2. 3.2 Critical Memory Access Latency
    3. 3.3 UDMA: DDR to DDR Data Copy
  7. 4Summary
  8. 5References

3.3 UDMA: DDR to DDR Data Copy

This section provides test results and observations for DDR to DDR block copy, using the Normal Capacity (NC) UDMA channel. This is detailed in Table 3-5.

Table 3-5 UDMA Channel Class
Description
Normal Capacity (NC)Provides baseline amount of descriptor and TR prefetch and Tx/Rx control and data buffering. An excellent choice for most peripheral transfers which are communicating with on-chip memories and DDR. With a buffer size of 192B, this FIFO depth allows for 3 read transactions, of 64B data bursts, per flight.

The following measurements are collected using bare-metal silicon verification tests on A53 executing out of DDR. Transfer descriptors and rings in DDR. Tests were done at 0.75V VDD_CORE, 1.25Ghz A53 cores, and 1600MT/s LPDDR4. Transfer sizes range from 1KiB to 512KiB.

The transfer capacity and latency of the NC UDMA channel, for buffer sizes up to 512 KiB, are shown in Table 3-6.

Table 3-6 UDMA: DDR to DDR Block Copy
Buffer Size (KiB)NC Channel Bandwidth (MiB/s)NC Channel Latency (μs)

1

204.73

4.77

2

283.47

6.89

4

349.40

11.18

8

387.91

20.14

16

420.48

37.16

32

436.33

71.62

64

444.49

140.61

128

448.77

278.54

256

450.82

554.54

512

452.10

1105.96