SPRUHX5I August   2014  – May 2024 TMS320F28374S , TMS320F28375S , TMS320F28375S-Q1 , TMS320F28376S , TMS320F28377S , TMS320F28377S-Q1 , TMS320F28378S , TMS320F28379S

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 C2000™ Microcontrollers Software Support
    1. 1.1 Introduction
    2. 1.2 C2000Ware Structure
    3. 1.3 Documentation
    4. 1.4 Devices
    5. 1.5 Libraries
    6. 1.6 Code Composer Studio™ Integrated Development Environment (IDE)
    7. 1.7 SysConfig and PinMUX Tool
  4. 2 C28x Processor
    1. 2.1 Introduction
    2. 2.2 C28X Related Collateral
    3. 2.3 Features
    4. 2.4 Floating-Point Unit
    5. 2.5 Trigonometric Math Unit (TMU)
    6. 2.6 Viterbi, Complex Math, and CRC Unit II (VCU-II)
  5. 3 System Control and Interrupt
    1. 3.1  Introduction
    2. 3.2  System Control Functional Description
      1. 3.2.1 Device Identification
      2. 3.2.2 Device Configuration Registers
    3. 3.3  Resets
      1. 3.3.1  Reset Sources
      2. 3.3.2  External Reset (XRS)
      3. 3.3.3  Power-On Reset (POR)
      4. 3.3.4  Debugger Reset (SYSRS)
      5. 3.3.5  Watchdog Reset (WDRS)
      6. 3.3.6  NMI Watchdog Reset (NMIWDRS)
      7. 3.3.7  DCSM Safe Code Copy Reset (SCCRESET)
      8. 3.3.8  Hibernate Reset (HIBRESET)
      9. 3.3.9  Hardware BIST Reset (HWBISTRS)
      10. 3.3.10 Test Reset (TRST)
    4. 3.4  Peripheral Interrupts
      1. 3.4.1 Interrupt Concepts
      2. 3.4.2 Interrupt Architecture
        1. 3.4.2.1 Peripheral Stage
        2. 3.4.2.2 PIE Stage
        3. 3.4.2.3 CPU Stage
      3. 3.4.3 Interrupt Entry Sequence
      4. 3.4.4 Configuring and Using Interrupts
        1. 3.4.4.1 Enabling Interrupts
        2. 3.4.4.2 Handling Interrupts
        3. 3.4.4.3 Disabling Interrupts
        4. 3.4.4.4 Nesting Interrupts
      5. 3.4.5 PIE Channel Mapping
        1. 3.4.5.1 PIE Interrupt Priority
          1. 3.4.5.1.1 Channel Priority
          2. 3.4.5.1.2 Group Priority
      6. 3.4.6 Vector Tables
    5. 3.5  Exceptions and Non-Maskable Interrupts
      1. 3.5.1 Configuring and Using NMIs
      2. 3.5.2 Emulation Considerations
      3. 3.5.3 NMI Sources
        1. 3.5.3.1 Missing Clock Detection
        2. 3.5.3.2 RAM Uncorrectable ECC Error
        3. 3.5.3.3 Flash Uncorrectable ECC Error
      4. 3.5.4 Illegal Instruction Trap (ITRAP)
    6. 3.6  Safety Features
      1. 3.6.1 Write Protection on Registers
        1. 3.6.1.1 LOCK Protection on System Configuration Registers
        2. 3.6.1.2 EALLOW Protection
      2. 3.6.2 Missing Clock Detection Logic
      3. 3.6.3 PLLSLIP Detection
      4. 3.6.4 CPU Vector Address Validity Check
      5. 3.6.5 NMIWDs
      6. 3.6.6 ECC and Parity Enabled RAMs, Shared RAMs Protection
      7. 3.6.7 ECC Enabled Flash Memory
      8. 3.6.8 ERRORSTS Pin
    7. 3.7  Clocking
      1. 3.7.1 Clock Sources
        1. 3.7.1.1 Primary Internal Oscillator (INTOSC2)
        2. 3.7.1.2 Backup Internal Oscillator (INTOSC1)
        3. 3.7.1.3 External Oscillator (XTAL)
        4. 3.7.1.4 Auxiliary Clock Input (AUXCLKIN)
      2. 3.7.2 Derived Clocks
        1. 3.7.2.1 Oscillator Clock (OSCCLK)
        2. 3.7.2.2 System PLL Output Clock (PLLRAWCLK)
        3. 3.7.2.3 Auxiliary Oscillator Clock (AUXOSCCLK)
        4. 3.7.2.4 Auxiliary PLL Output Clock (AUXPLLRAWCLK)
      3. 3.7.3 Device Clock Domains
        1. 3.7.3.1 System Clock (PLLSYSCLK)
        2. 3.7.3.2 CPU Clock (CPUCLK)
        3. 3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
        4. 3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
        5. 3.7.3.5 USB Auxiliary Clock (AUXPLLCLK)
        6. 3.7.3.6 CAN Bit Clock
        7. 3.7.3.7 CPU Timer2 Clock (TIMER2CLK)
      4. 3.7.4 XCLKOUT
      5. 3.7.5 Clock Connectivity
      6. 3.7.6 Clock Source and PLL Setup
        1. 3.7.6.1 Choosing PLL Settings
        2. 3.7.6.2 System Clock Setup
        3. 3.7.6.3 USB Auxiliary Clock Setup
        4. 3.7.6.4 Clock Configuration Examples
      7. 3.7.7 Clock (OSCCLK) Failure Detection
        1. 3.7.7.1 Missing Clock Detection Logic
    8. 3.8  32-Bit CPU Timers 0/1/2
    9. 3.9  Watchdog Timers
      1. 3.9.1 Servicing the Watchdog Timer
      2. 3.9.2 Minimum Window Check
      3. 3.9.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.9.4 Watchdog Operation in Low-Power Modes
      5. 3.9.5 Emulation Considerations
    10. 3.10 Low-Power Modes
      1. 3.10.1 IDLE
      2. 3.10.2 STANDBY
      3. 3.10.3 HALT
      4. 3.10.4 Hibernate (HIB)
    11. 3.11 Memory Controller Module
      1. 3.11.1 Functional Description
        1. 3.11.1.1 Dedicated RAM (Dx RAM)
        2. 3.11.1.2 Local Shared RAM (LSx RAM)
        3. 3.11.1.3 Global Shared RAM (GSx RAM)
        4. 3.11.1.4 Message RAM (CLA MSGRAM)
        5. 3.11.1.5 Access Arbitration
        6. 3.11.1.6 Access Protection
          1. 3.11.1.6.1 CPU Fetch Protection
          2. 3.11.1.6.2 CPU Write Protection
          3. 3.11.1.6.3 CPU Read Protection
          4. 3.11.1.6.4 CLA Fetch Protection
          5. 3.11.1.6.5 CLA Write Protection
          6. 3.11.1.6.6 CLA Read Protection
          7. 3.11.1.6.7 DMA Write Protection
        7. 3.11.1.7 Memory Error Detection, Correction and Error Handling
          1. 3.11.1.7.1 Error Detection and Correction
          2. 3.11.1.7.2 Error Handling
        8. 3.11.1.8 Application Test Hooks for Error Detection and Correction
        9. 3.11.1.9 RAM Initialization
    12. 3.12 Flash and OTP Memory
      1. 3.12.1  Features
      2. 3.12.2  Flash Tools
      3. 3.12.3  Default Flash Configuration
      4. 3.12.4  Flash Bank, One-Time Programmable (OTP) Memory, and Flash Pump
      5. 3.12.5  Flash Module Controller (FMC)
      6. 3.12.6  Flash and OTP Memory Power-Down Modes and Wakeup
      7. 3.12.7  Flash and OTP Memory Performance
      8. 3.12.8  Flash Read Interface
        1. 3.12.8.1 FMC Flash Read Interface
          1. 3.12.8.1.1 Standard Read Mode
          2. 3.12.8.1.2 Prefetch Mode
            1. 3.12.8.1.2.1 Data Cache
      9. 3.12.9  Erase/Program Flash
        1. 3.12.9.1 Erase
        2. 3.12.9.2 Program
        3. 3.12.9.3 Verify
      10. 3.12.10 Error Correction Code (ECC) Protection
        1. 3.12.10.1 Single-Bit Data Error
        2. 3.12.10.2 Uncorrectable Error
        3. 3.12.10.3 SECDED Logic Correctness Check
        4. 3.12.10.4 Reading ECC Memory From a Higher Address Space
      11. 3.12.11 Reserved Locations Within Flash and OTP Memory
      12. 3.12.12 Procedure to Change the Flash Control Registers
      13. 3.12.13 Simple Procedure to Modify an Application from RAM Configuration to Flash Configuration
      14. 3.12.14 Flash Pump Ownership Control
    13. 3.13 Dual Code Security Module (DCSM)
      1. 3.13.1 Functional Description
        1. 3.13.1.1 Emulation Code Security Logic (ECSL)
        2. 3.13.1.2 CPU Secure Logic
        3. 3.13.1.3 Execute-Only Protection
        4. 3.13.1.4 Password Lock
        5. 3.13.1.5 JTAG Lock
        6. 3.13.1.6 Link Pointer and Zone Select
          1. 3.13.1.6.1 C Code Example to get Zone Select Block Addr for Zone1
        7. 3.13.1.7 Flash and OTP Memory Erase/Program
        8. 3.13.1.8 Safe Copy Code
        9. 3.13.1.9 SafeCRC
      2. 3.13.2 CSM Impact on Other On-Chip Resources
      3. 3.13.3 Incorporating Code Security in User Applications
        1. 3.13.3.1 Environments That Require Security Unlocking
        2. 3.13.3.2 CSM Password Match Flow
        3. 3.13.3.3 Unsecuring Considerations for Zones With and Without Code Security
          1. 3.13.3.3.1 C Code Example to Unsecure C28x Zone1
          2. 3.13.3.3.2 C Code Example to Resecure C28x Zone1
        4. 3.13.3.4 Environments That Require ECSL Unlocking
        5. 3.13.3.5 ECSL Password Match Flow
        6. 3.13.3.6 ECSL Disable Considerations for any Zone
          1. 3.13.3.6.1 C Code Example to Disable ECSL for C28x-Zone1
        7. 3.13.3.7 Device Unique ID
    14. 3.14 JTAG
    15. 3.15 System Control Register Configuration Restrictions
    16. 3.16 Software
      1. 3.16.1 SYSCTL Examples
        1. 3.16.1.1 Missing clock detection (MCD)
        2. 3.16.1.2 XCLKOUT (External Clock Output) Configuration
      2. 3.16.2 TIMER Examples
        1. 3.16.2.1 CPU Timers
        2. 3.16.2.2 CPU Timers
      3. 3.16.3 MEMCFG Examples
      4. 3.16.4 INTERRUPT Examples
        1. 3.16.4.1 External Interrupts (ExternalInterrupt)
        2. 3.16.4.2 Multiple interrupt handling of I2C, SCI & SPI Digital Loopback
        3. 3.16.4.3 CPU Timer Interrupt Software Prioritization
        4. 3.16.4.4 EPWM Real-Time Interrupt
      5. 3.16.5 LPM Examples
      6. 3.16.6 WATCHDOG Examples
        1. 3.16.6.1 Watchdog
    17. 3.17 System Control Registers
      1. 3.17.1 System Control Base Addresses
        1. 3.17.1.1  CPUTIMER_REGS Registers
        2. 3.17.1.2  PIE_CTRL_REGS Registers
        3. 3.17.1.3  WD_REGS Registers
        4. 3.17.1.4  NMI_INTRUPT_REGS Registers
        5. 3.17.1.5  XINT_REGS Registers
        6. 3.17.1.6  SYNC_SOC_REGS Registers
        7. 3.17.1.7  DMA_CLA_SRC_SEL_REGS Registers
        8. 3.17.1.8  FLASH_PUMP_SEMAPHORE_REGS Registers
        9. 3.17.1.9  DEV_CFG_REGS Registers
        10. 3.17.1.10 CLK_CFG_REGS Registers
        11. 3.17.1.11 CPU_SYS_REGS Registers
        12. 3.17.1.12 ROM_PREFETCH_REGS Registers
        13. 3.17.1.13 DCSM_Z1_REGS Registers
        14. 3.17.1.14 DCSM_Z2_REGS Registers
        15. 3.17.1.15 DCSM_COMMON_REGS Registers
        16. 3.17.1.16 MEM_CFG_REGS Registers
        17. 3.17.1.17 ACCESS_PROTECTION_REGS Registers
        18. 3.17.1.18 MEMORY_ERROR_REGS Registers
        19. 3.17.1.19 ROM_WAIT_STATE_REGS Registers
        20. 3.17.1.20 FLASH_CTRL_REGS Registers
        21. 3.17.1.21 FLASH_ECC_REGS Registers
        22. 3.17.1.22 UID_REGS Registers
        23. 3.17.1.23 DCSM_Z1_OTP Registers
        24. 3.17.1.24 DCSM_Z2_OTP Registers
        25. 3.17.1.25 Register to Driverlib Function Mapping
          1. 3.17.1.25.1 CPUTIMER Registers to Driverlib Functions
          2. 3.17.1.25.2 ASYSCTL Registers to Driverlib Functions
          3. 3.17.1.25.3 PIE Registers to Driverlib Functions
          4. 3.17.1.25.4 SYSCTL Registers to Driverlib Functions
          5. 3.17.1.25.5 NMI Registers to Driverlib Functions
          6. 3.17.1.25.6 XINT Registers to Driverlib Functions
          7. 3.17.1.25.7 DCSM Registers to Driverlib Functions
          8. 3.17.1.25.8 MEMCFG Registers to Driverlib Functions
          9. 3.17.1.25.9 FLASH Registers to Driverlib Functions
  6. 4 ROM Code and Peripheral Booting
    1. 4.1  Introduction
    2. 4.2  Boot ROM Registers
    3. 4.3  Device Boot Sequence
    4. 4.4  Device Boot Modes
    5. 4.5  Configuring Boot Mode Pins
    6. 4.6  Configuring Get Boot Options
    7. 4.7  Configuring Emulation Boot Options
    8. 4.8  Device Boot Flow Diagrams
      1. 4.8.1 Emulation Boot Flow Diagrams
      2. 4.8.2 Standalone and Hibernate Boot Flow Diagrams
    9. 4.9  Device Reset and Exception Handling
      1. 4.9.1 Reset Causes and Handling
      2. 4.9.2 Exceptions and Interrupts Handling
    10. 4.10 Boot ROM Description
      1. 4.10.1  Entry Points
      2. 4.10.2  Wait Points
      3. 4.10.3  Memory Maps
        1. 4.10.3.1 Boot ROM Memory Map
        2. 4.10.3.2 CLA Data ROM Memory Map
        3. 4.10.3.3 Reserved RAM and Flash Memory-Map
        4. 4.10.3.4 ROM Tables
          1. 4.10.3.4.1 Boot ROM Tables
          2. 4.10.3.4.2 CLA ROM Tables
      4. 4.10.4  Boot Modes
        1. 4.10.4.1 Wait Boot Mode
        2. 4.10.4.2 SCI Boot Mode
        3. 4.10.4.3 SPI Boot Mode
        4. 4.10.4.4 I2C Boot Mode
        5. 4.10.4.5 Parallel Boot Mode
        6. 4.10.4.6 CAN Boot Mode
        7. 4.10.4.7 USB Boot Mode
      5. 4.10.5  Boot Data Stream Structure
        1. 4.10.5.1 Bootloader Data Stream Structure
          1. 4.10.5.1.1 Data Stream Structure 8-bit
      6. 4.10.6  GPIO Assignments
      7. 4.10.7  Secure ROM Function APIs
      8. 4.10.8  Clock Initializations
      9. 4.10.9  Wait State Configuration
      10. 4.10.10 Boot Status information
        1. 4.10.10.1 CPU Booting Status
      11. 4.10.11 ROM Version
  7. 5 Direct Memory Access (DMA)
    1. 5.1 Introduction
      1. 5.1.1 Features
      2. 5.1.2 Block Diagram
    2. 5.2 Architecture
      1. 5.2.1 Common Peripheral Architecture
      2. 5.2.2 Peripheral Interrupt Event Trigger Sources
      3. 5.2.3 DMA Bus
    3. 5.3 Address Pointer and Transfer Control
    4. 5.4 Pipeline Timing and Throughput
    5. 5.5 CPU and CLA Arbitration
    6. 5.6 Channel Priority
      1. 5.6.1 Round-Robin Mode
      2. 5.6.2 Channel 1 High-Priority Mode
    7. 5.7 Overrun Detection Feature
    8. 5.8 Software
      1. 5.8.1 DMA Examples
        1. 5.8.1.1 DMA GSRAM Transfer (dma_ex1_gsram_transfer)
        2. 5.8.1.2 DMA Transfer Shared Peripheral - C28X_DUAL
        3. 5.8.1.3 DMA Transfer for Shared Peripheral Example (CPU2) - C28X_DUAL
        4. 5.8.1.4 DMA GSRAM Transfer (dma_ex2_gsram_transfer)
    9. 5.9 DMA Registers
      1. 5.9.1 DMA Base Addresses
      2. 5.9.2 DMA_REGS Registers
      3. 5.9.3 DMA_CH_REGS Registers
      4. 5.9.4 DMA Registers to Driverlib Functions
  8. 6 Control Law Accelerator (CLA)
    1. 6.1 Introduction
      1. 6.1.1 Features
      2. 6.1.2 CLA Related Collateral
      3. 6.1.3 Block Diagram
    2. 6.2 CLA Interface
      1. 6.2.1 CLA Memory
      2. 6.2.2 CLA Memory Bus
      3. 6.2.3 Shared Peripherals and EALLOW Protection
      4. 6.2.4 CLA Tasks and Interrupt Vectors
      5. 6.2.5 CLA Software Interrupt to CPU
    3. 6.3 CLA and CPU Arbitration
      1. 6.3.1 CLA Message RAM
      2. 6.3.2 CLA Program Memory
      3. 6.3.3 CLA Data Memory
      4. 6.3.4 Peripheral Registers (ePWM, HRPWM, Comparator)
    4. 6.4 CLA Configuration and Debug
      1. 6.4.1 Building a CLA Application
      2. 6.4.2 Typical CLA Initialization Sequence
      3. 6.4.3 Debugging CLA Code
        1. 6.4.3.1 Breakpoint Support (MDEBUGSTOP)
      4. 6.4.4 CLA Illegal Opcode Behavior
      5. 6.4.5 Resetting the CLA
    5. 6.5 Pipeline
      1. 6.5.1 Pipeline Overview
      2. 6.5.2 CLA Pipeline Alignment
        1. 6.5.2.1 Code Fragment For MBCNDD, MCCNDD, or MRCNDD
        2.       335
        3. 6.5.2.2 Code Fragment for Loading MAR0 or MAR1
        4.       337
        5. 6.5.2.3 ADC Early Interrupt to CLA Response
      3. 6.5.3 Parallel Instructions
        1. 6.5.3.1 Math Operation with Parallel Load
        2. 6.5.3.2 Multiply with Parallel Add
      4. 6.5.4 CLA Task Execution Latency
    6. 6.6 Software
      1. 6.6.1 CLA Examples
        1. 6.6.1.1 CLA arcsine(x) using a lookup table (cla_asin_cpu01)
        2. 6.6.1.2 CLA arctangent(x) using a lookup table (cla_atan_cpu01)
    7. 6.7 Instruction Set
      1. 6.7.1 Instruction Descriptions
      2. 6.7.2 Addressing Modes and Encoding
      3. 6.7.3 Instructions
        1.       MABSF32 MRa, MRb
        2.       MADD32 MRa, MRb, MRc
        3.       MADDF32 MRa, #16FHi, MRb
        4.       MADDF32 MRa, MRb, #16FHi
        5.       MADDF32 MRa, MRb, MRc
        6.       MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa
        7.       MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        8.       MAND32 MRa, MRb, MRc
        9.       MASR32 MRa, #SHIFT
        10.       MBCNDD 16BitDest [, CNDF]
        11.       MCCNDD 16BitDest [, CNDF]
        12.       MCMP32 MRa, MRb
        13.       MCMPF32 MRa, MRb
        14.       MCMPF32 MRa, #16FHi
        15.       MDEBUGSTOP
        16.       MEALLOW
        17.       MEDIS
        18.       MEINVF32 MRa, MRb
        19.       MEISQRTF32 MRa, MRb
        20.       MF32TOI16 MRa, MRb
        21.       MF32TOI16R MRa, MRb
        22.       MF32TOI32 MRa, MRb
        23.       MF32TOUI16 MRa, MRb
        24.       MF32TOUI16R MRa, MRb
        25.       MF32TOUI32 MRa, MRb
        26.       MFRACF32 MRa, MRb
        27.       MI16TOF32 MRa, MRb
        28.       MI16TOF32 MRa, mem16
        29.       MI32TOF32 MRa, mem32
        30.       MI32TOF32 MRa, MRb
        31.       MLSL32 MRa, #SHIFT
        32.       MLSR32 MRa, #SHIFT
        33.       MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32
        34.       MMAXF32 MRa, MRb
        35.       MMAXF32 MRa, #16FHi
        36.       MMINF32 MRa, MRb
        37.       MMINF32 MRa, #16FHi
        38.       MMOV16 MARx, MRa, #16I
        39.       MMOV16 MARx, mem16
        40.       MMOV16 mem16, MARx
        41.       MMOV16 mem16, MRa
        42.       MMOV32 mem32, MRa
        43.       MMOV32 mem32, MSTF
        44.       MMOV32 MRa, mem32 [, CNDF]
        45.       MMOV32 MRa, MRb [, CNDF]
        46.       MMOV32 MSTF, mem32
        47.       MMOVD32 MRa, mem32
        48.       MMOVF32 MRa, #32F
        49.       MMOVI16 MARx, #16I
        50.       MMOVI32 MRa, #32FHex
        51.       MMOVIZ MRa, #16FHi
        52.       MMOVZ16 MRa, mem16
        53.       MMOVXI MRa, #16FLoHex
        54.       MMPYF32 MRa, MRb, MRc
        55.       MMPYF32 MRa, #16FHi, MRb
        56.       MMPYF32 MRa, MRb, #16FHi
        57.       MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf
        58.       MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        59.       MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        60.       MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf
        61.       MNEGF32 MRa, MRb[, CNDF]
        62.       MNOP
        63.       MOR32 MRa, MRb, MRc
        64.       MRCNDD [CNDF]
        65.       MSETFLG FLAG, VALUE
        66.       MSTOP
        67.       MSUB32 MRa, MRb, MRc
        68.       MSUBF32 MRa, MRb, MRc
        69.       MSUBF32 MRa, #16FHi, MRb
        70.       MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        71.       MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        72.       MSWAPF MRa, MRb [, CNDF]
        73.       MTESTTF CNDF
        74.       MUI16TOF32 MRa, mem16
        75.       MUI16TOF32 MRa, MRb
        76.       MUI32TOF32 MRa, mem32
        77.       MUI32TOF32 MRa, MRb
        78.       MXOR32 MRa, MRb, MRc
    8. 6.8 CLA Registers
      1. 6.8.1 CLA Base Addresses
      2. 6.8.2 CLA_REGS Registers
      3. 6.8.3 CLA_SOFTINT_REGS Registers
      4. 6.8.4 CLA Registers to Driverlib Functions
  9. 7 General-Purpose Input/Output (GPIO)
    1. 7.1  Introduction
      1. 7.1.1 GPIO Related Collateral
    2. 7.2  Configuration Overview
    3. 7.3  Digital General-Purpose I/O Control
    4. 7.4  Input Qualification
      1. 7.4.1 No Synchronization (Asynchronous Input)
      2. 7.4.2 Synchronization to SYSCLKOUT Only
      3. 7.4.3 Qualification Using a Sampling Window
    5. 7.5  USB Signals
    6. 7.6  SPI Signals
    7. 7.7  GPIO and Peripheral Muxing
      1. 7.7.1 GPIO Muxing
      2. 7.7.2 Peripheral Muxing
    8. 7.8  Internal Pullup Configuration Requirements
    9. 7.9  Software
      1. 7.9.1 GPIO Examples
        1. 7.9.1.1 Device GPIO Setup
        2. 7.9.1.2 Device GPIO Toggle
        3. 7.9.1.3 Device GPIO Interrupt
      2. 7.9.2 LED Examples
    10. 7.10 GPIO Registers
      1. 7.10.1 GPIO Base Addresses
      2. 7.10.2 GPIO_CTRL_REGS Registers
      3. 7.10.3 GPIO_DATA_REGS Registers
      4. 7.10.4 GPIO Registers to Driverlib Functions
  10. 8 Crossbar (X-BAR)
    1. 8.1 Input X-BAR
    2. 8.2 ePWM, CLB, and GPIO Output X-BAR
      1. 8.2.1 ePWM X-BAR
        1. 8.2.1.1 ePWM X-BAR Architecture
      2. 8.2.2 CLB X-BAR
        1. 8.2.2.1 CLB X-BAR Architecture
      3. 8.2.3 GPIO Output X-BAR
        1. 8.2.3.1 GPIO Output X-BAR Architecture
      4. 8.2.4 X-BAR Flags
    3. 8.3 XBAR Registers
      1. 8.3.1 XBAR Base Addresses
      2. 8.3.2 INPUT_XBAR_REGS Registers
      3. 8.3.3 XBAR_REGS Registers
      4. 8.3.4 EPWM_XBAR_REGS Registers
      5. 8.3.5 CLB_XBAR_REGS Registers
      6. 8.3.6 OUTPUT_XBAR_REGS Registers
      7. 8.3.7 Register to Driverlib Function Mapping
        1. 8.3.7.1 INPUTXBAR Registers to Driverlib Functions
        2. 8.3.7.2 XBAR Registers to Driverlib Functions
        3. 8.3.7.3 EPWMXBAR Registers to Driverlib Functions
        4. 8.3.7.4 CLBXBAR Registers to Driverlib Functions
        5. 8.3.7.5 OUTPUTXBAR Registers to Driverlib Functions
  11. 9 Analog Subsystem
    1. 9.1 Introduction
      1. 9.1.1 Features
      2. 9.1.2 Block Diagram
    2. 9.2 Optimizing Power-Up Time
    3. 9.3 Analog Subsystem Registers
      1. 9.3.1 Analog Subsystem Base Addresses
      2. 9.3.2 ANALOG_SUBSYS_REGS Registers
  12. 10Analog-to-Digital Converter (ADC)
    1. 10.1  Introduction
      1. 10.1.1 ADC Related Collateral
      2. 10.1.2 Features
      3. 10.1.3 Block Diagram
    2. 10.2  ADC Configurability
      1. 10.2.1 Clock Configuration
      2. 10.2.2 Resolution
      3. 10.2.3 Voltage Reference
        1. 10.2.3.1 External Reference Mode
      4. 10.2.4 Signal Mode
      5. 10.2.5 Expected Conversion Results
      6. 10.2.6 Interpreting Conversion Results
    3. 10.3  SOC Principle of Operation
      1. 10.3.1 SOC Configuration
      2. 10.3.2 Trigger Operation
      3. 10.3.3 ADC Acquisition (Sample and Hold) Window
      4. 10.3.4 ADC Input Models
      5. 10.3.5 Channel Selection
    4. 10.4  SOC Configuration Examples
      1. 10.4.1 Single Conversion from ePWM Trigger
      2. 10.4.2 Oversampled Conversion from ePWM Trigger
      3. 10.4.3 Multiple Conversions from CPU Timer Trigger
      4. 10.4.4 Software Triggering of SOCs
    5. 10.5  ADC Conversion Priority
    6. 10.6  Burst Mode
      1. 10.6.1 Burst Mode Example
      2. 10.6.2 Burst Mode Priority Example
    7. 10.7  EOC and Interrupt Operation
      1. 10.7.1 Interrupt Overflow
      2. 10.7.2 Continue to Interrupt Mode
      3. 10.7.3 Early Interrupt Configuration Mode
    8. 10.8  Post-Processing Blocks
      1. 10.8.1 PPB Offset Correction
      2. 10.8.2 PPB Error Calculation
      3. 10.8.3 PPB Limit Detection and Zero-Crossing Detection
      4. 10.8.4 PPB Sample Delay Capture
    9. 10.9  Opens/Shorts Detection Circuit (OSDETECT)
      1. 10.9.1 Implementation
      2. 10.9.2 Detecting an Open Input Pin
      3. 10.9.3 Detecting a Shorted Input Pin
    10. 10.10 Power-Up Sequence
    11. 10.11 ADC Calibration
      1. 10.11.1 ADC Zero Offset Calibration
      2. 10.11.2 ADC Calibration Routines in OTP Memory
    12. 10.12 ADC Timings
      1. 10.12.1 ADC Timing Diagrams
    13. 10.13 Additional Information
      1. 10.13.1 Ensuring Synchronous Operation
        1. 10.13.1.1 Basic Synchronous Operation
        2. 10.13.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 10.13.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 10.13.1.4 Synchronous Operation with Different Resolutions
        5. 10.13.1.5 Non-overlapping Conversions
      2. 10.13.2 Choosing an Acquisition Window Duration
      3. 10.13.3 Achieving Simultaneous Sampling
      4. 10.13.4 Result Register Mapping
      5. 10.13.5 Internal Temperature Sensor
      6. 10.13.6 Designing an External Reference Circuit
    14. 10.14 Software
      1. 10.14.1 ADC Examples
        1. 10.14.1.1  ADC Software Triggering
        2. 10.14.1.2  ADC ePWM Triggering
        3. 10.14.1.3  ADC Temperature Sensor Conversion
        4. 10.14.1.4  ADC Synchronous SOC Software Force (adc_soc_software_sync)
        5. 10.14.1.5  ADC Continuous Triggering (adc_soc_continuous)
        6. 10.14.1.6  ADC PPB Offset (adc_ppb_offset)
        7. 10.14.1.7  ADC PPB Limits (adc_ppb_limits)
        8. 10.14.1.8  ADC PPB Delay Capture (adc_ppb_delay)
        9. 10.14.1.9  ADC ePWM Triggering Multiple SOC
        10. 10.14.1.10 ADC Burst Mode
        11. 10.14.1.11 ADC Burst Mode Oversampling
        12. 10.14.1.12 ADC SOC Oversampling
        13. 10.14.1.13 ADC PPB PWM trip (adc_ppb_pwm_trip)
    15. 10.15 ADC Registers
      1. 10.15.1 ADC Base Addresses
      2. 10.15.2 ADC_RESULT_REGS Registers
      3. 10.15.3 ADC_REGS Registers
      4. 10.15.4 ADC Registers to Driverlib Functions
  13. 11Buffered Digital-to-Analog Converter (DAC)
    1. 11.1 Introduction
      1. 11.1.1 DAC Related Collateral
      2. 11.1.2 Features
      3. 11.1.3 Block Diagram
    2. 11.2 Using the DAC
      1. 11.2.1 Initialization Sequence
      2. 11.2.2 DAC Offset Adjustment
      3. 11.2.3 EPWMSYNCPER Signal
    3. 11.3 Lock Registers
    4. 11.4 Software
      1. 11.4.1 DAC Examples
        1. 11.4.1.1 Buffered DAC Enable
        2. 11.4.1.2 Buffered DAC Random
        3. 11.4.1.3 Buffered DAC Sine (buffdac_sine)
    5. 11.5 DAC Registers
      1. 11.5.1 DAC Base Addresses
      2. 11.5.2 DAC_REGS Registers
      3. 11.5.3 DAC Registers to Driverlib Functions
  14. 12Comparator Subsystem (CMPSS)
    1. 12.1 Introduction
      1. 12.1.1 CMPSS Related Collateral
      2. 12.1.2 Features
      3. 12.1.3 Block Diagram
    2. 12.2 Comparator
    3. 12.3 Reference DAC
    4. 12.4 Ramp Generator
      1. 12.4.1 Ramp Generator Overview
      2. 12.4.2 Ramp Generator Behavior
      3. 12.4.3 Ramp Generator Behavior at Corner Cases
    5. 12.5 Digital Filter
      1. 12.5.1 Filter Initialization Sequence
    6. 12.6 Using the CMPSS
      1. 12.6.1 LATCHCLR and EPWMSYNCPER Signals
      2. 12.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 12.6.3 Calibrating the CMPSS
      4. 12.6.4 Enabling and Disabling the CMPSS Clock
    7. 12.7 Software
      1. 12.7.1 CMPSS Examples
        1. 12.7.1.1 CMPSS Asynchronous Trip
        2. 12.7.1.2 CMPSS Digital Filter Configuration
    8. 12.8 CMPSS Registers
      1. 12.8.1 CMPSS Base Addresses
      2. 12.8.2 CMPSS_REGS Registers
      3. 12.8.3 CMPSS Registers to Driverlib Functions
  15. 13Sigma Delta Filter Module (SDFM)
    1. 13.1  Introduction
      1. 13.1.1 SDFM Related Collateral
      2. 13.1.2 Features
      3. 13.1.3 Block Diagram
    2. 13.2  Configuring Device Pins
    3. 13.3  Input Control Unit
    4. 13.4  Sinc Filter
      1. 13.4.1 Data Rate and Latency of the Sinc Filter
    5. 13.5  Data (Primary) Filter Unit
      1. 13.5.1 32-bit or 16-bit Data Filter Output Representation
      2. 13.5.2 SDSYNC Event
    6. 13.6  Comparator (Secondary) Filter Unit
      1. 13.6.1 Higher Threshold (HLT) Comparator
      2. 13.6.2 Lower Threshold (LLT) Comparator
    7. 13.7  Theoretical SDFM Filter Output
    8. 13.8  Interrupt Unit
      1. 13.8.1 SDFM (SDINT) Interrupt Sources
    9. 13.9  Register Descriptions
    10. 13.10 Software
      1. 13.10.1 SDFM Examples
    11. 13.11 SDFM Registers
      1. 13.11.1 SDFM Base Addresses
      2. 13.11.2 SDFM_REGS Registers
      3. 13.11.3 SDFM Registers to Driverlib Functions
  16. 14Enhanced Pulse Width Modulator (ePWM)
    1. 14.1  Introduction
      1. 14.1.1 EPWM Related Collateral
      2. 14.1.2 Submodule Overview
    2. 14.2  Configuring Device Pins
    3. 14.3  ePWM Modules Overview
    4. 14.4  Time-Base (TB) Submodule
      1. 14.4.1 Purpose of the Time-Base Submodule
      2. 14.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 14.4.3 Calculating PWM Period and Frequency
        1. 14.4.3.1 Time-Base Period Shadow Register
        2. 14.4.3.2 Time-Base Clock Synchronization
        3. 14.4.3.3 Time-Base Counter Synchronization
      4. 14.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 14.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
      6. 14.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 14.4.7 Global Load
        1. 14.4.7.1 Global Load Pulse Pre-Scalar
        2. 14.4.7.2 One-Shot Load Mode
        3. 14.4.7.3 One-Shot Sync Mode
    5. 14.5  Counter-Compare (CC) Submodule
      1. 14.5.1 Purpose of the Counter-Compare Submodule
      2. 14.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 14.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 14.5.4 Count Mode Timing Waveforms
    6. 14.6  Action-Qualifier (AQ) Submodule
      1. 14.6.1 Purpose of the Action-Qualifier Submodule
      2. 14.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 14.6.3 Action-Qualifier Event Priority
      4. 14.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 14.6.5 Configuration Requirements for Common Waveforms
    7. 14.7  Dead-Band Generator (DB) Submodule
      1. 14.7.1 Purpose of the Dead-Band Submodule
      2. 14.7.2 Dead-band Submodule Additional Operating Modes
      3. 14.7.3 Operational Highlights for the Dead-Band Submodule
    8. 14.8  PWM Chopper (PC) Submodule
      1. 14.8.1 Purpose of the PWM Chopper Submodule
      2. 14.8.2 Operational Highlights for the PWM Chopper Submodule
      3. 14.8.3 Waveforms
        1. 14.8.3.1 One-Shot Pulse
        2. 14.8.3.2 Duty Cycle Control
    9. 14.9  Trip-Zone (TZ) Submodule
      1. 14.9.1 Purpose of the Trip-Zone Submodule
      2. 14.9.2 Operational Highlights for the Trip-Zone Submodule
        1. 14.9.2.1 Trip-Zone Configurations
      3. 14.9.3 Generating Trip Event Interrupts
    10. 14.10 Event-Trigger (ET) Submodule
      1. 14.10.1 Operational Overview of the ePWM Event-Trigger Submodule
    11. 14.11 Digital Compare (DC) Submodule
      1. 14.11.1 Purpose of the Digital Compare Submodule
      2. 14.11.2 Enhanced Trip Action Using CMPSS
      3. 14.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 14.11.4 Operation Highlights of the Digital Compare Submodule
        1. 14.11.4.1 Digital Compare Events
        2. 14.11.4.2 Event Filtering
        3. 14.11.4.3 Valley Switching
    12. 14.12 ePWM Crossbar (X-BAR)
    13. 14.13 Applications to Power Topologies
      1. 14.13.1  Overview of Multiple Modules
      2. 14.13.2  Key Configuration Capabilities
      3. 14.13.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 14.13.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 14.13.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 14.13.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 14.13.7  Practical Applications Using Phase Control Between PWM Modules
      8. 14.13.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 14.13.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 14.13.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 14.13.11 Controlling H-Bridge LLC Resonant Converter
    14. 14.14 High-Resolution Pulse Width Modulator (HRPWM)
      1. 14.14.1 Operational Description of HRPWM
        1. 14.14.1.1 Controlling the HRPWM Capabilities
        2. 14.14.1.2 HRPWM Source Clock
        3. 14.14.1.3 Configuring the HRPWM
        4. 14.14.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 14.14.1.5 Principle of Operation
          1. 14.14.1.5.1 Edge Positioning
          2. 14.14.1.5.2 Scaling Considerations
          3. 14.14.1.5.3 Duty Cycle Range Limitation
          4. 14.14.1.5.4 High-Resolution Period
            1. 14.14.1.5.4.1 High-Resolution Period Configuration
        6. 14.14.1.6 Deadband High-Resolution Operation
        7. 14.14.1.7 Scale Factor Optimizing Software (SFO)
        8. 14.14.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 14.14.1.8.1 #Defines for HRPWM Header Files
          2. 14.14.1.8.2 Implementing a Simple Buck Converter
            1. 14.14.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 14.14.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 14.14.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 14.14.1.8.3.1 PWM DAC Function Initialization Code
            2. 14.14.1.8.3.2 PWM DAC Function Run-Time Code
      2. 14.14.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 14.14.2.1 Scale Factor Optimizer Function - int SFO()
        2. 14.14.2.2 Software Usage
          1. 14.14.2.2.1 A Sample of How to Add "Include" Files
          2.        735
          3. 14.14.2.2.2 Declaring an Element
          4.        737
          5. 14.14.2.2.3 Initializing With a Scale Factor Value
          6.        739
          7. 14.14.2.2.4 SFO Function Calls
    15. 14.15 ePWM Registers
      1. 14.15.1 ePWM Base Addresses
      2. 14.15.2 EPWM_REGS Registers
      3. 14.15.3 Register to Driverlib Function Mapping
        1. 14.15.3.1 EPWM Registers to Driverlib Functions
        2. 14.15.3.2 HRPWM Registers to Driverlib Functions
  17. 15Enhanced Capture (eCAP)
    1. 15.1 Introduction
      1. 15.1.1 Features
      2. 15.1.2 ECAP Related Collateral
    2. 15.2 Description
    3. 15.3 Configuring Device Pins for the eCAP
    4. 15.4 Capture and APWM Operating Mode
    5. 15.5 Capture Mode Description
      1. 15.5.1  Event Prescaler
      2. 15.5.2  Edge Polarity Select and Qualifier
      3. 15.5.3  Continuous/One-Shot Control
      4. 15.5.4  32-Bit Counter and Phase Control
      5. 15.5.5  CAP1-CAP4 Registers
      6. 15.5.6  eCAP Synchronization
        1. 15.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 15.5.7  Interrupt Control
      8. 15.5.8  DMA Interrupt
      9. 15.5.9  Shadow Load and Lockout Control
      10. 15.5.10 APWM Mode Operation
    6. 15.6 Application of the eCAP Module
      1. 15.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 15.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 15.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 15.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 15.7 Application of the APWM Mode
      1. 15.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 15.8 Software
      1. 15.8.1 ECAP Examples
        1. 15.8.1.1 eCAP APWM Example
        2. 15.8.1.2 eCAP Capture PWM Example
        3. 15.8.1.3 eCAP APWM Phase-shift Example
        4. 15.8.1.4 eCAP Software Sync Example
    9. 15.9 eCAP Registers
      1. 15.9.1 eCAP Base Addresses
      2. 15.9.2 ECAP_REGS Registers
      3. 15.9.3 ECAP Registers to Driverlib Functions
  18. 16Enhanced Quadrature Encoder Pulse (eQEP)
    1. 16.1  Introduction
      1. 16.1.1 EQEP Related Collateral
    2. 16.2  Configuring Device Pins
    3. 16.3  Description
      1. 16.3.1 EQEP Inputs
      2. 16.3.2 Functional Description
      3. 16.3.3 eQEP Memory Map
    4. 16.4  Quadrature Decoder Unit (QDU)
      1. 16.4.1 Position Counter Input Modes
        1. 16.4.1.1 Quadrature Count Mode
        2. 16.4.1.2 Direction-Count Mode
        3. 16.4.1.3 Up-Count Mode
        4. 16.4.1.4 Down-Count Mode
      2. 16.4.2 eQEP Input Polarity Selection
      3. 16.4.3 Position-Compare Sync Output
    5. 16.5  Position Counter and Control Unit (PCCU)
      1. 16.5.1 Position Counter Operating Modes
        1. 16.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM]=00)
        2. 16.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM]=01)
        3. 16.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 16.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 16.5.2 Position Counter Latch
        1. 16.5.2.1 Index Event Latch
        2. 16.5.2.2 Strobe Event Latch
      3. 16.5.3 Position Counter Initialization
      4. 16.5.4 eQEP Position-compare Unit
    6. 16.6  eQEP Edge Capture Unit
    7. 16.7  eQEP Watchdog
    8. 16.8  eQEP Unit Timer Base
    9. 16.9  eQEP Interrupt Structure
    10. 16.10 eQEP Registers
      1. 16.10.1 eQEP Base Addresses
      2. 16.10.2 EQEP_REGS Registers
      3. 16.10.3 EQEP Registers to Driverlib Functions
  19. 17Serial Peripheral Interface (SPI)
    1. 17.1 Introduction
      1. 17.1.1 Features
      2. 17.1.2 SPI Related Collateral
      3. 17.1.3 Block Diagram
    2. 17.2 System-Level Integration
      1. 17.2.1 SPI Module Signals
      2. 17.2.2 Configuring Device Pins
        1. 17.2.2.1 GPIOs Required for High-Speed Mode
      3. 17.2.3 SPI Interrupts
      4. 17.2.4 DMA Support
    3. 17.3 SPI Operation
      1. 17.3.1  Introduction to Operation
      2. 17.3.2  Master Mode
      3. 17.3.3  Slave Mode
      4. 17.3.4  Data Format
        1. 17.3.4.1 Transmission of Bit from SPIRXBUF
      5. 17.3.5  Baud Rate Selection
        1. 17.3.5.1 Baud Rate Determination
        2. 17.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
      6. 17.3.6  SPI Clocking Schemes
      7. 17.3.7  SPI FIFO Description
      8. 17.3.8  SPI DMA Transfers
        1. 17.3.8.1 Transmitting Data Using SPI with DMA
        2. 17.3.8.2 Receiving Data Using SPI with DMA
      9. 17.3.9  SPI High-Speed Mode
      10. 17.3.10 SPI 3-Wire Mode Description
    4. 17.4 Programming Procedure
      1. 17.4.1 Initialization Upon Reset
      2. 17.4.2 Configuring the SPI
      3. 17.4.3 Configuring the SPI for High-Speed Mode
      4. 17.4.4 Data Transfer Example
      5. 17.4.5 SPI 3-Wire Mode Code Examples
        1. 17.4.5.1 3-Wire Master Mode Transmit
        2.       852
          1. 17.4.5.2.1 3-Wire Master Mode Receive
        3.       854
          1. 17.4.5.2.1 3-Wire Slave Mode Transmit
        4.       856
          1. 17.4.5.2.1 3-Wire Slave Mode Receive
      6. 17.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 17.5 Software
      1. 17.5.1 SPI Examples
        1. 17.5.1.1 SPI Digital Loopback
        2. 17.5.1.2 SPI Digital Loopback with FIFO Interrupts
        3. 17.5.1.3 SPI Digital External Loopback without FIFO Interrupts
        4. 17.5.1.4 SPI Digital External Loopback with FIFO Interrupts
        5. 17.5.1.5 SPI Digital Loopback with DMA
        6. 17.5.1.6 SPI EEPROM
        7. 17.5.1.7 SPI DMA EEPROM
    6. 17.6 SPI Registers
      1. 17.6.1 SPI Base Addresses
      2. 17.6.2 SPI_REGS Registers
      3. 17.6.3 SPI Registers to Driverlib Functions
  20. 18Serial Communications Interface (SCI)
    1. 18.1  Introduction
      1. 18.1.1 Features
      2. 18.1.2 SCI Related Collateral
      3. 18.1.3 Block Diagram
    2. 18.2  Architecture
    3. 18.3  SCI Module Signal Summary
    4. 18.4  Configuring Device Pins
    5. 18.5  Multiprocessor and Asynchronous Communication Modes
    6. 18.6  SCI Programmable Data Format
    7. 18.7  SCI Multiprocessor Communication
      1. 18.7.1 Recognizing the Address Byte
      2. 18.7.2 Controlling the SCI TX and RX Features
      3. 18.7.3 Receipt Sequence
    8. 18.8  Idle-Line Multiprocessor Mode
      1. 18.8.1 Idle-Line Mode Steps
      2. 18.8.2 Block Start Signal
      3. 18.8.3 Wake-Up Temporary (WUT) Flag
        1. 18.8.3.1 Sending a Block Start Signal
      4. 18.8.4 Receiver Operation
    9. 18.9  Address-Bit Multiprocessor Mode
      1. 18.9.1 Sending an Address
    10. 18.10 SCI Communication Format
      1. 18.10.1 Receiver Signals in Communication Modes
      2. 18.10.2 Transmitter Signals in Communication Modes
    11. 18.11 SCI Port Interrupts
      1. 18.11.1 Break Detect
    12. 18.12 SCI Baud Rate Calculations
    13. 18.13 SCI Enhanced Features
      1. 18.13.1 SCI FIFO Description
      2. 18.13.2 SCI Auto-Baud
      3. 18.13.3 Autobaud-Detect Sequence
    14. 18.14 Software
      1. 18.14.1 SCI Examples
    15. 18.15 SCI Registers
      1. 18.15.1 SCI Base Addresses
      2. 18.15.2 SCI_REGS Registers
      3. 18.15.3 SCI Registers to Driverlib Functions
  21. 19Inter-Integrated Circuit Module (I2C)
    1. 19.1 Introduction
      1. 19.1.1 I2C Related Collateral
      2. 19.1.2 Features
      3. 19.1.3 Features Not Supported
      4. 19.1.4 Functional Overview
      5. 19.1.5 Clock Generation
      6. 19.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 19.1.6.1 Formula for the Master Clock Period
    2. 19.2 Configuring Device Pins
    3. 19.3 I2C Module Operational Details
      1. 19.3.1  Input and Output Voltage Levels
      2. 19.3.2  Selecting Pullup Resistors
      3. 19.3.3  Data Validity
      4. 19.3.4  Operating Modes
      5. 19.3.5  I2C Module START and STOP Conditions
      6. 19.3.6  Non-repeat Mode versus Repeat Mode
      7. 19.3.7  Serial Data Formats
        1. 19.3.7.1 7-Bit Addressing Format
        2. 19.3.7.2 10-Bit Addressing Format
        3. 19.3.7.3 Free Data Format
        4. 19.3.7.4 Using a Repeated START Condition
      8. 19.3.8  Clock Synchronization
      9. 19.3.9  Arbitration
      10. 19.3.10 Digital Loopback Mode
      11. 19.3.11 NACK Bit Generation
    4. 19.4 Interrupt Requests Generated by the I2C Module
      1. 19.4.1 Basic I2C Interrupt Requests
      2. 19.4.2 I2C FIFO Interrupts
    5. 19.5 Resetting or Disabling the I2C Module
    6. 19.6 Software
      1. 19.6.1 I2C Examples
        1. 19.6.1.1 C28x-I2C Library source file for FIFO interrupts
        2. 19.6.1.2 C28x-I2C Library source file for FIFO using polling
        3. 19.6.1.3 C28x-I2C Library source file for FIFO interrupts
        4. 19.6.1.4 I2C Digital Loopback with FIFO Interrupts
        5. 19.6.1.5 I2C EEPROM
        6. 19.6.1.6 I2C Digital External Loopback with FIFO Interrupts
        7. 19.6.1.7 I2C EEPROM
        8. 19.6.1.8 I2C controller target communication using FIFO interrupts
        9. 19.6.1.9 I2C EEPROM
    7. 19.7 I2C Registers
      1. 19.7.1 I2C Base Addresses
      2. 19.7.2 I2C_REGS Registers
      3. 19.7.3 I2C Registers to Driverlib Functions
  22. 20Multichannel Buffered Serial Port (McBSP)
    1. 20.1  Introduction
      1. 20.1.1 MCBSP Related Collateral
      2. 20.1.2 Features of the McBSPs
      3. 20.1.3 McBSP Pins/Signals
        1. 20.1.3.1 McBSP Generic Block Diagram
    2. 20.2  Configuring Device Pins
    3. 20.3  McBSP Operation
      1. 20.3.1 Data Transfer Process of McBSPs
        1. 20.3.1.1 Data Transfer Process for Word Length of 8, 12, or 16 Bits
        2. 20.3.1.2 Data Transfer Process for Word Length of 20, 24, or 32 Bits
      2. 20.3.2 Companding (Compressing and Expanding) Data
        1. 20.3.2.1 Companding Formats
        2. 20.3.2.2 Capability to Compand Internal Data
        3. 20.3.2.3 Reversing Bit Order: Option to Transfer LSB First
      3. 20.3.3 Clocking and Framing Data
        1. 20.3.3.1 Clocking
        2. 20.3.3.2 Serial Words
        3. 20.3.3.3 Frames and Frame Synchronization
        4. 20.3.3.4 Generating Transmit and Receive Interrupts
          1. 20.3.3.4.1 Detecting Frame-Synchronization Pulses, Even in Reset State
        5. 20.3.3.5 Ignoring Frame-Synchronization Pulses
        6. 20.3.3.6 Frame Frequency
        7. 20.3.3.7 Maximum Frame Frequency
      4. 20.3.4 Frame Phases
        1. 20.3.4.1 Number of Phases, Words, and Bits Per Frame
        2. 20.3.4.2 Single-Phase Frame Example
        3. 20.3.4.3 Dual-Phase Frame Example
        4. 20.3.4.4 Implementing the AC97 Standard With a Dual-Phase Frame
      5. 20.3.5 McBSP Reception
      6. 20.3.6 McBSP Transmission
      7. 20.3.7 Interrupts and DMA Events Generated by a McBSP
    4. 20.4  McBSP Sample Rate Generator
      1. 20.4.1 Block Diagram
        1. 20.4.1.1 Clock Generation in the Sample Rate Generator
        2. 20.4.1.2 Choosing an Input Clock
        3. 20.4.1.3 Choosing a Polarity for the Input Clock
        4. 20.4.1.4 Choosing a Frequency for the Output Clock (CLKG)
          1. 20.4.1.4.1 CLKG Frequency
        5. 20.4.1.5 Keeping CLKG Synchronized to External MCLKR
      2. 20.4.2 Frame Synchronization Generation in the Sample Rate Generator
        1. 20.4.2.1 Choosing the Width of the Frame-Synchronization Pulse on FSG
        2. 20.4.2.2 Controlling the Period Between the Starting Edges of Frame-Synchronization Pulses on FSG
        3. 20.4.2.3 Keeping FSG Synchronized to an External Clock
      3. 20.4.3 Synchronizing Sample Rate Generator Outputs to an External Clock
        1. 20.4.3.1 Operating the Transmitter Synchronously with the Receiver
        2. 20.4.3.2 Synchronization Examples
      4. 20.4.4 Reset and Initialization Procedure for the Sample Rate Generator
    5. 20.5  McBSP Exception/Error Conditions
      1. 20.5.1 Types of Errors
      2. 20.5.2 Overrun in the Receiver
        1. 20.5.2.1 Example of Overrun Condition
        2. 20.5.2.2 Example of Preventing Overrun Condition
      3. 20.5.3 Unexpected Receive Frame-Synchronization Pulse
        1. 20.5.3.1 Possible Responses to Receive Frame-Synchronization Pulses
        2. 20.5.3.2 Example of Unexpected Receive Frame-Synchronization Pulse
        3. 20.5.3.3 Preventing Unexpected Receive Frame-Synchronization Pulses
      4. 20.5.4 Overwrite in the Transmitter
        1. 20.5.4.1 Example of Overwrite Condition
        2. 20.5.4.2 Preventing Overwrites
      5. 20.5.5 Underflow in the Transmitter
        1. 20.5.5.1 Example of the Underflow Condition
        2. 20.5.5.2 Example of Preventing Underflow Condition
      6. 20.5.6 Unexpected Transmit Frame-Synchronization Pulse
        1. 20.5.6.1 Possible Responses to Transmit Frame-Synchronization Pulses
        2. 20.5.6.2 Example of Unexpected Transmit Frame-Synchronization Pulse
        3. 20.5.6.3 Preventing Unexpected Transmit Frame-Synchronization Pulses
    6. 20.6  Multichannel Selection Modes
      1. 20.6.1 Channels, Blocks, and Partitions
      2. 20.6.2 Multichannel Selection
      3. 20.6.3 Configuring a Frame for Multichannel Selection
      4. 20.6.4 Using Two Partitions
        1. 20.6.4.1 Assigning Blocks to Partitions A and B
        2. 20.6.4.2 Reassigning Blocks During Reception/Transmission
      5. 20.6.5 Using Eight Partitions
      6. 20.6.6 Receive Multichannel Selection Mode
      7. 20.6.7 Transmit Multichannel Selection Modes
        1. 20.6.7.1 Disabling/Enabling Versus Masking/Unmasking
        2. 20.6.7.2 Activity on McBSP Pins for Different Values of XMCM
      8. 20.6.8 Using Interrupts Between Block Transfers
    7. 20.7  SPI Operation Using the Clock Stop Mode
      1. 20.7.1 SPI Protocol
      2. 20.7.2 Clock Stop Mode
      3. 20.7.3 Enable and Configure the Clock Stop Mode
      4. 20.7.4 Clock Stop Mode Timing Diagrams
      5. 20.7.5 Procedure for Configuring a McBSP for SPI Operation
      6. 20.7.6 McBSP as the SPI Master
      7. 20.7.7 McBSP as an SPI Slave
    8. 20.8  Receiver Configuration
      1. 20.8.1  Programming the McBSP Registers for the Desired Receiver Operation
      2. 20.8.2  Resetting and Enabling the Receiver
        1. 20.8.2.1 Reset Considerations
      3. 20.8.3  Set the Receiver Pins to Operate as McBSP Pins
      4. 20.8.4  Digital Loopback Mode
      5. 20.8.5  Clock Stop Mode
      6. 20.8.6  Receive Multichannel Selection Mode
      7. 20.8.7  Receive Frame Phases
      8. 20.8.8  Receive Word Lengths
        1. 20.8.8.1 Word Length Bits
      9. 20.8.9  Receive Frame Length
        1. 20.8.9.1 Selected Frame Length
      10. 20.8.10 Receive Frame-Synchronization Ignore Function
        1. 20.8.10.1 Unexpected Frame-Synchronization Pulses and the Frame-Synchronization Ignore Function
        2. 20.8.10.2 Examples of Effects of RFIG
      11. 20.8.11 Receive Companding Mode
        1. 20.8.11.1 Companding
        2. 20.8.11.2 Format of Expanded Data
        3. 20.8.11.3 Companding Internal Data
        4. 20.8.11.4 Option to Receive LSB First
      12. 20.8.12 Receive Data Delay
        1. 20.8.12.1 Data Delay
        2. 20.8.12.2 0-Bit Data Delay
        3. 20.8.12.3 2-Bit Data Delay
      13. 20.8.13 Receive Sign-Extension and Justification Mode
        1. 20.8.13.1 Sign-Extension and the Justification
      14. 20.8.14 Receive Interrupt Mode
      15. 20.8.15 Receive Frame-Synchronization Mode
        1. 20.8.15.1 Receive Frame-Synchronization Modes
      16. 20.8.16 Receive Frame-Synchronization Polarity
        1. 20.8.16.1 Frame-Synchronization Pulses, Clock Signals, and Their Polarities
        2. 20.8.16.2 Frame-Synchronization Period and the Frame-Synchronization Pulse Width
      17. 20.8.17 Receive Clock Mode
        1. 20.8.17.1 Selecting a Source for the Receive Clock and a Data Direction for the MCLKR Pin
      18. 20.8.18 Receive Clock Polarity
        1. 20.8.18.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
      19. 20.8.19 SRG Clock Divide-Down Value
        1. 20.8.19.1 Sample Rate Generator Clock Divider
      20. 20.8.20 SRG Clock Synchronization Mode
      21. 20.8.21 SRG Clock Mode (Choose an Input Clock)
      22. 20.8.22 SRG Input Clock Polarity
        1. 20.8.22.1 Using CLKXP/CLKRP to Choose an Input Clock Polarity
    9. 20.9  Transmitter Configuration
      1. 20.9.1  Programming the McBSP Registers for the Desired Transmitter Operation
      2. 20.9.2  Resetting and Enabling the Transmitter
        1. 20.9.2.1 Reset Considerations
      3. 20.9.3  Set the Transmitter Pins to Operate as McBSP Pins
      4. 20.9.4  Digital Loopback Mode
      5. 20.9.5  Clock Stop Mode
      6. 20.9.6  Transmit Multichannel Selection Mode
      7. 20.9.7  XCERs Used in the Transmit Multichannel Selection Mode
      8. 20.9.8  Transmit Frame Phases
      9. 20.9.9  Transmit Word Lengths
        1. 20.9.9.1 Word Length Bits
      10. 20.9.10 Transmit Frame Length
        1. 20.9.10.1 Selected Frame Length
      11. 20.9.11 Enable/Disable the Transmit Frame-Synchronization Ignore Function
        1. 20.9.11.1 Unexpected Frame-Synchronization Pulses and Frame-Synchronization Ignore
        2. 20.9.11.2 Examples Showing the Effects of XFIG
      12. 20.9.12 Transmit Companding Mode
        1. 20.9.12.1 Companding
        2. 20.9.12.2 Format for Data To Be Compressed
        3. 20.9.12.3 Capability to Compand Internal Data
        4. 20.9.12.4 Option to Transmit LSB First
      13. 20.9.13 Transmit Data Delay
        1. 20.9.13.1 Data Delay
        2. 20.9.13.2 0-Bit Data Delay
        3. 20.9.13.3 2-Bit Data Delay
      14. 20.9.14 Transmit DXENA Mode
      15. 20.9.15 Transmit Interrupt Mode
      16. 20.9.16 Transmit Frame-Synchronization Mode
        1. 20.9.16.1 Other Considerations
      17. 20.9.17 Transmit Frame-Synchronization Polarity
        1. 20.9.17.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
      18. 20.9.18 SRG Frame-Synchronization Period and Pulse Width
        1. 20.9.18.1 Frame-Synchronization Period and Frame-Synchronization Pulse Width
      19. 20.9.19 Transmit Clock Mode
        1. 20.9.19.1 Selecting a Source for the Transmit Clock and a Data Direction for the MCLKX pin
        2. 20.9.19.2 Other Considerations
      20. 20.9.20 Transmit Clock Polarity
        1. 20.9.20.1 Frame Synchronization Pulses, Clock Signals, and Their Polarities
    10. 20.10 Emulation and Reset Considerations
      1. 20.10.1 McBSP Emulation Mode
      2. 20.10.2 Resetting and Initializing McBSPs
        1. 20.10.2.1 McBSP Pin States: DSP Reset Versus Receiver/Transmitter Reset
        2. 20.10.2.2 Device Reset, McBSP Reset, and Sample Rate Generator Reset
        3. 20.10.2.3 McBSP Initialization Procedure
        4. 20.10.2.4 Resetting the Transmitter While the Receiver is Running
          1. 20.10.2.4.1 Resetting and Configuring McBSP Transmitter While McBSP Receiver Running
    11. 20.11 Data Packing Examples
      1. 20.11.1 Data Packing Using Frame Length and Word Length
      2. 20.11.2 Data Packing Using Word Length and the Frame-Synchronization Ignore Function
    12. 20.12 Interrupt Generation
      1. 20.12.1 McBSP Receive Interrupt Generation
      2. 20.12.2 McBSP Transmit Interrupt Generation
      3. 20.12.3 Error Flags
    13. 20.13 McBSP Modes
    14. 20.14 Special Case: External Device is the Transmit Frame Master
    15. 20.15 Software
      1. 20.15.1 MCBSP Examples
    16. 20.16 McBSP Registers
      1. 20.16.1 McBSP Base Addresses
      2. 20.16.2 McBSP_REGS Registers
      3. 20.16.3 MCBSP Registers to Driverlib Functions
  23. 21Controller Area Network (CAN)
    1. 21.1  Introduction
      1. 21.1.1 DCAN Related Collateral
      2. 21.1.2 Features
      3. 21.1.3 Block Diagram
        1. 21.1.3.1 CAN Core
        2. 21.1.3.2 Message Handler
        3. 21.1.3.3 Message RAM
        4. 21.1.3.4 Registers and Message Object Access (IFx)
    2. 21.2  Functional Description
      1. 21.2.1 Configuring Device Pins
      2. 21.2.2 Address/Data Bus Bridge
    3. 21.3  Operating Modes
      1. 21.3.1 Initialization
      2. 21.3.2 CAN Message Transfer (Normal Operation)
        1. 21.3.2.1 Disabled Automatic Retransmission
        2. 21.3.2.2 Auto-Bus-On
      3. 21.3.3 Test Modes
        1. 21.3.3.1 Silent Mode
        2. 21.3.3.2 Loopback Mode
        3. 21.3.3.3 External Loopback Mode
        4. 21.3.3.4 Loopback Combined with Silent Mode
    4. 21.4  Multiple Clock Source
    5. 21.5  Interrupt Functionality
      1. 21.5.1 Message Object Interrupts
      2. 21.5.2 Status Change Interrupts
      3. 21.5.3 Error Interrupts
      4. 21.5.4 Peripheral Interrupt Expansion (PIE) Module Nomenclature for DCAN Interrupts
      5. 21.5.5 Interrupt Topologies
    6. 21.6  Parity Check Mechanism
      1. 21.6.1 Behavior on Parity Error
    7. 21.7  Debug Mode
    8. 21.8  Module Initialization
    9. 21.9  Configuration of Message Objects
      1. 21.9.1 Configuration of a Transmit Object for Data Frames
      2. 21.9.2 Configuration of a Transmit Object for Remote Frames
      3. 21.9.3 Configuration of a Single Receive Object for Data Frames
      4. 21.9.4 Configuration of a Single Receive Object for Remote Frames
      5. 21.9.5 Configuration of a FIFO Buffer
    10. 21.10 Message Handling
      1. 21.10.1  Message Handler Overview
      2. 21.10.2  Receive/Transmit Priority
      3. 21.10.3  Transmission of Messages in Event Driven CAN Communication
      4. 21.10.4  Updating a Transmit Object
      5. 21.10.5  Changing a Transmit Object
      6. 21.10.6  Acceptance Filtering of Received Messages
      7. 21.10.7  Reception of Data Frames
      8. 21.10.8  Reception of Remote Frames
      9. 21.10.9  Reading Received Messages
      10. 21.10.10 Requesting New Data for a Receive Object
      11. 21.10.11 Storing Received Messages in FIFO Buffers
      12. 21.10.12 Reading from a FIFO Buffer
    11. 21.11 CAN Bit Timing
      1. 21.11.1 Bit Time and Bit Rate
        1. 21.11.1.1 Synchronization Segment
        2. 21.11.1.2 Propagation Time Segment
        3. 21.11.1.3 Phase Buffer Segments and Synchronization
        4. 21.11.1.4 Oscillator Tolerance Range
      2. 21.11.2 Configuration of the CAN Bit Timing
        1. 21.11.2.1 Calculation of the Bit Timing Parameters
        2. 21.11.2.2 Example for Bit Timing at High Baudrate
        3. 21.11.2.3 Example for Bit Timing at Low Baudrate
    12. 21.12 Message Interface Register Sets
      1. 21.12.1 Message Interface Register Sets 1 and 2 (IF1 and IF2)
      2. 21.12.2 Message Interface Register Set 3 (IF3)
    13. 21.13 Message RAM
      1. 21.13.1 Structure of Message Objects
      2. 21.13.2 Addressing Message Objects in RAM
      3. 21.13.3 Message RAM Representation in Debug Mode
    14. 21.14 Software
      1. 21.14.1 CAN Examples
    15. 21.15 CAN Registers
      1. 21.15.1 CAN Base Addresses
      2. 21.15.2 CAN_REGS Registers
      3. 21.15.3 CAN Registers to Driverlib Functions
  24. 22Universal Serial Bus (USB) Controller
    1. 22.1 Introduction
      1. 22.1.1 Features
      2. 22.1.2 USB Related Collateral
      3. 22.1.3 Block Diagram
        1. 22.1.3.1 Signal Description
        2. 22.1.3.2 VBus Recommendations
    2. 22.2 Functional Description
      1. 22.2.1 Operation as a Device
        1. 22.2.1.1 Control and Configurable Endpoints
          1. 22.2.1.1.1 IN Transactions as a Device
          2. 22.2.1.1.2 Out Transactions as a Device
          3. 22.2.1.1.3 Scheduling
          4. 22.2.1.1.4 Additional Actions
          5. 22.2.1.1.5 Device Mode Suspend
          6. 22.2.1.1.6 Start of Frame
          7. 22.2.1.1.7 USB Reset
          8. 22.2.1.1.8 Connect/Disconnect
      2. 22.2.2 Operation as a Host
        1. 22.2.2.1 Endpoint Registers
        2. 22.2.2.2 IN Transactions as a Host
        3. 22.2.2.3 OUT Transactions as a Host
        4. 22.2.2.4 Transaction Scheduling
        5. 22.2.2.5 USB Hubs
        6. 22.2.2.6 Babble
        7. 22.2.2.7 Host SUSPEND
        8. 22.2.2.8 USB RESET
        9. 22.2.2.9 Connect/Disconnect
      3. 22.2.3 DMA Operation
      4. 22.2.4 Address/Data Bus Bridge
    3. 22.3 Initialization and Configuration
      1. 22.3.1 Pin Configuration
      2. 22.3.2 Endpoint Configuration
    4. 22.4 USB Global Interrupts
    5. 22.5 Software
      1. 22.5.1 USB Examples
    6. 22.6 USB Registers
      1. 22.6.1 USB Base Address
      2. 22.6.2 USB Register Map
      3. 22.6.3 Register Descriptions
        1. 22.6.3.1  USB Device Functional Address Register (USBFADDR), offset 0x000
        2. 22.6.3.2  USB Power Management Register (USBPOWER), offset 0x001
        3. 22.6.3.3  USB Transmit Interrupt Status Register
        4. 22.6.3.4  USB Receive Interrupt Status Register
        5. 22.6.3.5  USB Transmit Interrupt Enable Register
        6. 22.6.3.6  USB Receive Interrupt Enable Register
        7. 22.6.3.7  USB General Interrupt Status Register (USBIS), offset 0x00A
        8. 22.6.3.8  USB Interrupt Enable Register (USBIE), offset 0x00B
        9. 22.6.3.9  USB Frame Value Register (USBFRAME), offset 0x00C
        10. 22.6.3.10 USB Endpoint Index Register (USBEPIDX), offset 0x00E
        11. 22.6.3.11 USB Test Mode Register (USBTEST), offset 0x00F
        12. 22.6.3.12 USB FIFO Endpoint n Register (USBFIFO[0]-USBFIFO[3])
        13. 22.6.3.13 USB Device Control Register (USBDEVCTL), offset 0x060
        14. 22.6.3.14 USB Transmit Dynamic FIFO Sizing Register (USBTXFIFOSZ), offset 0x062
        15. 22.6.3.15 USB Receive Dynamic FIFO Sizing Register (USBRXFIFOSZ), offset 0x063
        16. 22.6.3.16 USB Transmit FIFO Start Address Register (USBTXFIFOADD), offset 0x064
        17. 22.6.3.17 USB Receive FIFO Start Address Register (USBRXFIFOADD), offset 0x066
        18. 22.6.3.18 USB Connect Timing Register (USBCONTIM), offset 0x07A
        19. 22.6.3.19 USB Full-Speed Last Transaction to End of Frame Timing Register (USBFSEOF), offset 0x07D
        20. 22.6.3.20 USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF), offset 0x07E
        21. 22.6.3.21 USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[0]-USBTXFUNCADDR[n])
        22. 22.6.3.22 USB Transmit Hub Address Endpoint n Registers (USBTXHUBADDR[0]-USBTXHUBADDR[n])
        23. 22.6.3.23 USB Transmit Hub Port Endpoint n Registers (USBTXHUBPORT[0]-USBTXHUBPORT[n])
        24. 22.6.3.24 USB Receive Functional Address Endpoint n Registers (USBRXFUNCADDR[1]-USBRXFUNCADDR[n)
        25. 22.6.3.25 USB Receive Hub Address Endpoint n Registers (USBRXHUBADDR[1]-USBRXHUBADDR[n])
        26. 22.6.3.26 USB Receive Hub Port Endpoint n Register (USBRXHUBPORT[1]-USBRXHUBPORT[n])
        27. 22.6.3.27 USB Maximum Transmit Data Endpoint n Registers (USBTXMAXP[1]-USBTXMAXP[n])
        28. 22.6.3.28 USB Control and Status Endpoint 0 Low Register (USBCSRL0), offset 0x102
        29. 22.6.3.29 USB Control and Status Endpoint 0 High Register (USBCSRH0), offset 0x103
        30. 22.6.3.30 USB Receive Byte Count Endpoint 0 Register (USBCOUNT0), offset 0x108
        31. 22.6.3.31 USB Type Endpoint 0 Register (USBTYPE0), offset 0x10A
        32. 22.6.3.32 USB NAK Limit Register (USBNAKLMT), offset 0x10B
        33. 22.6.3.33 USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[1]-USBTXCSRL[n])
        34. 22.6.3.34 USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[1]-USBTXCSRH[n])
        35. 22.6.3.35 USB Maximum Receive Data Endpoint n Registers (USBRXMAXP[1]-USBRXMAXP[n])
        36. 22.6.3.36 USB Receive Control and Status Endpoint n Low Register (USBRXCSRL[1]-USBRXCSRL[n])
        37. 22.6.3.37 USB Receive Control and Status Endpoint n High Register (USBRXCSRH[1]-USBRXCSRH[n])
        38. 22.6.3.38 USB Receive Byte Count Endpoint n Register (USBRXCOUNT[1]-USBRXCOUNT[n])
        39. 22.6.3.39 USB Host Transmit Configure Type Endpoint n Registers (USBTXTYPE[1]-USBTXTYPE[n])
        40. 22.6.3.40 USB Host Transmit Interval Endpoint n Registers (USBTXINTERVAL[1]-USBTXINTERVAL[n])
        41. 22.6.3.41 USB Host Configure Receive Type Endpoint n Register (USBRXTYPE[1]-USBRXTYPE[n])
        42. 22.6.3.42 USB Host Receive Polling Interval Endpoint n Registers (USBRXINTERVAL[1]-USBRXINTERVAL[n])
        43. 22.6.3.43 USB Request Packet Count in Block Transfer Endpoint n Registers (USBRQPKTCOUNT[1]-USBRQPKTCOUNT[n])
        44. 22.6.3.44 USB Receive Double Packet Buffer Disable Register (USBRXDPKTBUFDIS), offset 0x340
        45. 22.6.3.45 USB Transmit Double Packet Buffer Disable Register (USBTXDPKTBUFDIS), offset 0x342
        46. 22.6.3.46 USB External Power Control Register (USBEPC), offset 0x400
        47. 22.6.3.47 USB External Power Control Raw Interrupt Status Register (USBEPCRIS), offset 0x404
        48. 22.6.3.48 USB External Power Control Interrupt Mask Register (USBEPCIM), offset 0x408
        49. 22.6.3.49 USB External Power Control Interrupt Status and Clear Register (USBEPCISC), offset 0x40C
        50. 22.6.3.50 USB Device RESUME Raw Interrupt Status Register (USBDRRIS), offset 0x410
        51. 22.6.3.51 USB Device RESUME Raw Interrupt Mask Register (USBDRIM), offset 0x414
        52. 22.6.3.52 USB Device RESUME Interrupt Status and Clear Register (USBDRISC), offset 0x418
        53. 22.6.3.53 USB General-Purpose Control and Status Register (USBGPCS), offset 0x41C
        54. 22.6.3.54 USB DMA Select Register (USBDMASEL), offset 0x450
      4. 22.6.4 USB Registers to Driverlib Functions
  25. 23Universal Parallel Port (uPP)
    1. 23.1 Introduction
      1. 23.1.1 Features Supported
    2. 23.2 Configuring Device Pins
    3. 23.3 Functional Description
      1. 23.3.1 Functional Block Diagram
      2. 23.3.2 Data Flow
      3. 23.3.3 Clock Generation and Control
    4. 23.4 IO Interface and System Requirements
      1. 23.4.1  Pin Multiplexing
      2. 23.4.2  Internal DMA Controller Description
        1. 23.4.2.1 DMA Programming Concepts
        2. 23.4.2.2 Data Interleave Mode
      3. 23.4.3  Protocol Description
        1. 23.4.3.1 DATA[7:0] Signals
        2. 23.4.3.2 START Signal
        3. 23.4.3.3 ENABLE
        4. 23.4.3.4 WAIT Signal
        5. 23.4.3.5 CLOCK Signal
        6. 23.4.3.6 Signal Timing Diagrams
      4. 23.4.4  Data Format
      5. 23.4.5  Reset Considerations
        1. 23.4.5.1 Software Reset
        2. 23.4.5.2 Hardware Reset
      6. 23.4.6  Interrupt Support
        1. 23.4.6.1 End of Line (EOL) Event
        2. 23.4.6.2 End of Window (EOW) Event
        3. 23.4.6.3 Underrun or Overflow (UOR) Event
        4. 23.4.6.4 DMA Programming Error (DPE) Event
      7. 23.4.7  Emulation Considerations
      8. 23.4.8  Transmit and Receive FIFOs
      9. 23.4.9  Transmit and Receive Data (MSG) RAM
      10. 23.4.10 Initialization and Operation
        1. 23.4.10.1 System Tuning Tips
    5. 23.5 UPP Registers
      1. 23.5.1 UPP Base Addresses
      2. 23.5.2 UPP_REGS Registers
      3. 23.5.3 UPP Registers to Driverlib Functions
  26. 24External Memory Interface (EMIF)
    1. 24.1 Introduction
      1. 24.1.1 Purpose of the Peripheral
      2. 24.1.2 EMIF Related Collateral
      3. 24.1.3 Features
        1. 24.1.3.1 Asynchronous Memory Support
        2. 24.1.3.2 Synchronous DRAM Memory Support
      4. 24.1.4 Functional Block Diagram
      5. 24.1.5 Configuring Device Pins
    2. 24.2 EMIF Module Architecture
      1. 24.2.1  EMIF Clock Control
      2. 24.2.2  EMIF Requests
      3. 24.2.3  EMIF Signal Descriptions
      4. 24.2.4  EMIF Signal Multiplexing Control
      5. 24.2.5  SDRAM Controller and Interface
        1. 24.2.5.1  SDRAM Commands
        2. 24.2.5.2  Interfacing to SDRAM
        3. 24.2.5.3  SDRAM Configuration Registers
        4. 24.2.5.4  SDRAM Auto-Initialization Sequence
        5. 24.2.5.5  SDRAM Configuration Procedure
        6. 24.2.5.6  EMIF Refresh Controller
          1. 24.2.5.6.1 Determining the Appropriate Value for the RR Field
        7. 24.2.5.7  Self-Refresh Mode
        8. 24.2.5.8  Power-Down Mode
        9. 24.2.5.9  SDRAM Read Operation
        10. 24.2.5.10 SDRAM Write Operations
        11. 24.2.5.11 Mapping from Logical Address to EMIF Pins
      6. 24.2.6  Asynchronous Controller and Interface
        1. 24.2.6.1 Interfacing to Asynchronous Memory
        2. 24.2.6.2 Accessing Larger Asynchronous Memories
        3. 24.2.6.3 Configuring EMIF for Asynchronous Accesses
        4. 24.2.6.4 Read and Write Operations in Normal Mode
          1. 24.2.6.4.1 Asynchronous Read Operations (Normal Mode)
          2. 24.2.6.4.2 Asynchronous Write Operations (Normal Mode)
        5. 24.2.6.5 Read and Write Operation in Select Strobe Mode
          1. 24.2.6.5.1 Asynchronous Read Operations (Select Strobe Mode)
          2. 24.2.6.5.2 Asynchronous Write Operations (Select Strobe Mode)
        6. 24.2.6.6 Extended Wait Mode and the EM1WAIT Pin
      7. 24.2.7  Data Bus Parking
      8. 24.2.8  Reset and Initialization Considerations
      9. 24.2.9  Interrupt Support
        1. 24.2.9.1 Interrupt Events
      10. 24.2.10 DMA Event Support
      11. 24.2.11 EMIF Signal Multiplexing
      12. 24.2.12 Memory Map
      13. 24.2.13 Priority and Arbitration
      14. 24.2.14 System Considerations
        1. 24.2.14.1 Asynchronous Request Times
      15. 24.2.15 Power Management
        1. 24.2.15.1 Power Management Using Self-Refresh Mode
        2. 24.2.15.2 Power Management Using Power Down Mode
      16. 24.2.16 Emulation Considerations
    3. 24.3 Example Configuration
      1. 24.3.1 Hardware Interface
      2. 24.3.2 Software Configuration
        1. 24.3.2.1 Configuring the SDRAM Interface
          1. 24.3.2.1.1 PLL Programming for EMIF to K4S641632H-TC(L)70 Interface
          2. 24.3.2.1.2 SDRAM Timing Register (SDRAM_TR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          3. 24.3.2.1.3 SDRAM Self Refresh Exit Timing Register (SDR_EXT_TMNG) Settings for EMIF to K4S641632H-TC(L)70 Interface
          4. 24.3.2.1.4 SDRAM Refresh Control Register (SDRAM_RCR) Settings for EMIF to K4S641632H-TC(L)70 Interface
          5. 24.3.2.1.5 SDRAM Configuration Register (SDRAM_CR) Settings for EMIF to K4S641632H-TC(L)70 Interface
        2. 24.3.2.2 Configuring the Flash Interface
          1. 24.3.2.2.1 Asynchronous 1 Configuration Register (ASYNC_CS2_CFG) Settings for EMIF to LH28F800BJE-PTTL90 Interface
    4. 24.4 EMIF Registers
      1. 24.4.1 EMIF Base Addresses
      2. 24.4.2 EMIF_REGS Registers
      3. 24.4.3 EMIF1_CONFIG_REGS Registers
      4. 24.4.4 EMIF2_CONFIG_REGS Registers
      5. 24.4.5 EMIF Registers to Driverlib Functions
  27. 25Configurable Logic Block (CLB)
    1. 25.1 Introduction
      1. 25.1.1 CLB Related Collateral
    2. 25.2 Description
      1. 25.2.1 CLB Clock
    3. 25.3 CLB Input/Output Connection
      1. 25.3.1 Overview
      2. 25.3.2 CLB Input Selection
      3. 25.3.3 CLB Output Selection
      4. 25.3.4 CLB Output Signal Multiplexer
    4. 25.4 CLB Tile
      1. 25.4.1 Static Switch Block
      2. 25.4.2 Counter Block
        1. 25.4.2.1 Counter Description
        2. 25.4.2.2 Counter Operation
      3. 25.4.3 FSM Block
      4. 25.4.4 LUT4 Block
      5. 25.4.5 Output LUT Block
      6. 25.4.6 High Level Controller (HLC)
        1. 25.4.6.1 High Level Controller Events
        2. 25.4.6.2 High Level Controller Instructions
        3. 25.4.6.3 <Src> and <Dest>
        4. 25.4.6.4 Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
    5. 25.5 CPU Interface
      1. 25.5.1 Register Description
      2. 25.5.2 Non-Memory Mapped Registers
    6. 25.6 DMA Access
    7. 25.7 Software
      1. 25.7.1 CLB Examples
        1. 25.7.1.1  CLB Empty Project
        2. 25.7.1.2  CLB Combinational Logic
        3. 25.7.1.3  CLB GPIO Input Filter
        4. 25.7.1.4  CLB Auxilary PWM
        5. 25.7.1.5  CLB PWM Protection
        6. 25.7.1.6  CLB Event Window
        7. 25.7.1.7  CLB Signal Generator
        8. 25.7.1.8  CLB State Machine
        9. 25.7.1.9  CLB External Signal AND Gate
        10. 25.7.1.10 CLB Timer
        11. 25.7.1.11 CLB Timer Two States
        12. 25.7.1.12 CLB Interrupt Tag
        13. 25.7.1.13 CLB Output Intersect
        14. 25.7.1.14 CLB PUSH PULL
        15. 25.7.1.15 CLB Multi Tile
        16. 25.7.1.16 CLB Tile to Tile Delay
        17. 25.7.1.17 CLB based One-shot PWM
        18. 25.7.1.18 CLB Trip Zone Timestamp
    8. 25.8 CLB Registers
      1. 25.8.1 CLB Base Addresses
      2. 25.8.2 CLB_LOGIC_CONFIG_REGS Registers
      3. 25.8.3 CLB_LOGIC_CONTROL_REGS Registers
      4. 25.8.4 CLB_DATA_EXCHANGE_REGS Registers
      5. 25.8.5 CLB Registers to Driverlib Functions
  28. 26Revision History

22.6.2 USB Register Map

Table 22-4 lists the registers. All addresses given are relative to the USB base address of 0x0000_5E00.

Note: The USB controller clock must be enabled before the registers can be programmed (see the System Control and Interrupt chapter).
Table 22-4 Universal Serial Bus (USB) Controller Register Map
Offset Acronym Register Name Section
0x000 USBFADDR(1) USB Device Functional Address Go
0x001 USBPOWER(1)(2) USB Power Go
0x002 USBTXIS(1)(2) USB Transmit Interrupt Status Go
0x004 USBRXIS(1)(2) USB Receive Interrupt Status Go
0x006 USBTXIE(1)(2) USB Transmit Interrupt Enable Go
0x008 USBRXIE(1)(2) USB Receive Interrupt Enable Go
0x00A USBIS(1)(2) USB General Interrupt Status Go
0x00B USBIE(1)(2) USB Interrupt Enable Go
0x00C USBFRAME(1)(2) USB Frame Value Go
0x00E USBEPIDX(1)(2) USB Endpoint Index Go
0x00F USBTEST(1)(2) USB Test Mode Go
0x020 USBFIFO0(1)(2) USB FIFO Endpoint 0 Go
0x024 USBFIFO1(1)(2) USB FIFO Endpoint 1 Go
0x028 USBFIFO2(1)(2) USB FIFO Endpoint 2 Go
0x02C USBFIFO3(1)(2) USB FIFO Endpoint 3 Go
0x060 USBDEVCTL(2) USB Device Control Go
0x062 USBTXFIFOSZ(1)(2) USB Transmit Dynamic FIFO Sizing Go
0x063 USBRXFIFOSZ(1)(2) USB Receive Dynamic FIFO Sizing Go
0x064 USBTXFIFOADD(1)(2) USB Transmit FIFO Start Address Go
0x066 USBRXFIFOADD(1)(2) USB Receive FIFO Start Address Go
0x07A USBCONTIM(1)(2) USB Connect Timing Go
0x07D USBFSEOF(1)(2) USB Full-Speed Last Transaction to End of Frame Timing Go
0x07E USBLSEOF(1)(2) USB Low-Speed Last Transaction to End of Frame Timing Go
0x080 USBTXFUNCADDR0(2) USB Transmit Functional Address Endpoint 0 Go
0x082 USBTXHUBADDR0(2) USB Transmit Hub Address Endpoint 0 Go
0x083 USBTXHUBPORT0(2) USB Transmit Hub Port Endpoint 0 Go
0x088 USBTXFUNCADDR1(2) USB Transmit Functional Address Endpoint 1 Go
0x08A USBTXHUBADDR1(2) USB Transmit Hub Address Endpoint 1 Go
0x08B USBTXHUBPORT1(2) USB Transmit Hub Port Endpoint 1 Go
0x08C USBRXFUNCADDR1(2) USB Receive Functional Address Endpoint 1 Go
0x08E USBRXHUBADDR1(2) USB Receive Hub Address Endpoint 1 Go
0x08F USBRXHUBPORT1(2) USB Receive Hub Port Endpoint 1 Go
0x090 USBTXFUNCADDR2(2) USB Transmit Functional Address Endpoint 2 Go
0x092 USBTXHUBADDR2(2) USB Transmit Hub Address Endpoint 2 Go
0x093 USBTXHUBPORT2(2) USB Transmit Hub Port Endpoint 2 Go
0x094 USBRXFUNCADDR2(2) USB Receive Functional Address Endpoint 2 Go
0x096 USBRXHUBADDR2(2) USB Receive Hub Address Endpoint 2 Go
0x097 USBRXHUBPORT2(2) USB Receive Hub Port Endpoint 2 Go
0x098 USBTXFUNCADDR3(2) USB Transmit Functional Address Endpoint 3 Go
0x09A USBTXHUBADDR3(2) USB Transmit Hub Address Endpoint 3 Go
0x09B USBTXHUBPORT3(2) USB Transmit Hub Port Endpoint 3 Go
0x09C USBRXFUNCADDR3(2) USB Receive Functional Address Endpoint 3 Go
0x09E USBRXHUBADDR3(2) USB Receive Hub Address Endpoint 3 Go
0x09F USBRXHUBPORT3(2) USB Receive Hub Port Endpoint 3 Go
0xA0 USBTXFUNCADDR4(2) USB Transmit Functional Address Endpoint 4 Go
0xA2 USBTXHUBADDR4(2) USB Transmit Hub Address Endpoint 4 Go
0xA3 USBTXHUBPORT4(2) USB Transmit Hub Port Endpoint 4 Go
0xA4 USBRXFUNCADDR4(2) USB Receive Functional Address Endpoint 4 Go
0xA6 USBRXHUBADDR4(2) USB Receive Hub Address Endpoint 4 Go
0xA7 USBRXHUBPORT4(2) USB Receive Hub Port Endpoint 4 Go
0xA8 USBTXFUNCADDR5(2) USB Transmit Functional Address Endpoint 5 Go
0xAA USBTXHUBADDR5(2) USB Transmit Hub Address Endpoint 5 Go
0xAB USBTXHUBPORT5(2) USB Transmit Hub Port Endpoint 5 Go
0xAC USBRXFUNCADDR4(2) USB Receive Functional Address Endpoint 5 Go
0xAE USBRXHUBADDR5(2) USB Receive Hub Address Endpoint 5 Go
0xAF USBRXHUBPORT5(2) USB Receive Hub Port Endpoint 5 Go
0xB0 USBTXFUNCADDR6(2) USB Transmit Functional Address Endpoint 6 Go
0xB2 USBTXHUBADDR6(2) USB Transmit Hub Address Endpoint 6 Go
0xB3 USBTXHUBPORT6(2) USB Transmit Hub Port Endpoint 6 Go
0xB4 USBRXFUNCADDR6(2) USB Receive Functional Address Endpoint 6 Go
0xB6 USBRXHUBADDR6(2) USB Receive Hub Address Endpoint 6 Go
0xB7 USBRXHUBPORT6(2) USB Receive Hub Port Endpoint 6 Go
0xB8 USBTXFUNCADDR7(2) USB Transmit Functional Address Endpoint 7 Go
0xBA USBTXHUBADDR7(2) USB Transmit Hub Address Endpoint 7 Go
0xBB USBTXHUBPORT7(2) USB Transmit Hub Port Endpoint 7 Go
0xBC USBRXFUNCADDR7(2) USB Receive Functional Address Endpoint 7 Go
0xBE USBRXHUBADDR7(2) USB Receive Hub Address Endpoint 7 Go
0xBF USBRXHUBPORT7(2) USB Receive Hub Port Endpoint 7 Go
0x0C0 USBTXFUNCADDR8(2) USB Transmit Functional Address Endpoint 8 Go
0x0C2 USBTXHUBADDR8(2) USB Transmit Hub Address Endpoint 8 Go
0x0C3 USBTXHUBPORT8(2) USB Transmit Hub Port Endpoint 8 Go
0x0C4 USBRXFUNCADDR8(2) USB Receive Functional Address Endpoint 8 Go
0x0C6 USBRXHUBADDR8(2) USB Receive Hub Address Endpoint 8 Go
0x0C7 USBRXHUBPORT8(2) USB Receive Hub Port Endpoint 8 Go
0xC8 USBTXFUNCADDR9(2) USB Transmit Functional Address Endpoint 9 Go
0x0CA USBTXHUBADDR9(2) USB Transmit Hub Address Endpoint 9 Go
0x0CB USBTXHUBPORT9(2) USB Transmit Hub Port Endpoint 9 Go
0x0CC USBRXFUNCADDR9(2) USB Receive Functional Address Endpoint 9 Go
0x0CE USBRXHUBADDR9(2) USB Receive Hub Address Endpoint 9 Go
0x0CF USBRXHUBPORT9(2) USB Receive Hub Port Endpoint 9 Go
0x0D0 USBTXFUNCADDR10(2) USB Transmit Functional Address Endpoint 10 Go
0x0D2 USBTXHUBADDR10(2) USB Transmit Hub Address Endpoint 10 Go
0x0D3 USBTXHUBPORT10(2) USB Transmit Hub Port Endpoint 10 Go
0x0D4 USBRXFUNCADDR10(2) USB Receive Functional Address Endpoint 10 Go
0x0D6 USBRXHUBADDR10(2) USB Receive Hub Address Endpoint 10 Go
0x0D7 USBRXHUBPORT10(2) USB Receive Hub Port Endpoint 10 Go
0x0D8 USBTXFUNCADDR11(2) USB Transmit Functional Address Endpoint 11 Go
0x0DA USBTXHUBADDR11(2) USB Transmit Hub Address Endpoint 11 Go
0x0DB USBTXHUBPORT11(2) USB Transmit Hub Port Endpoint 11 Go
0x0DC USBRXFUNCADDR11(2) USB Receive Functional Address Endpoint 11 Go
0x0DE USBRXHUBADDR11(2) USB Receive Hub Address Endpoint 11 Go
0x0DF USBRXHUBPORT11(2) USB Receive Hub Port Endpoint 11 Go
0x0E0 USBTXFUNCADDR12(2) USB Transmit Functional Address Endpoint 12 Go
0x0E2 USBTXHUBADDR12(2) USB Transmit Hub Address Endpoint 12 Go
0x0E3 USBTXHUBPORT12(2) USB Transmit Hub Port Endpoint 12 Go
0x0E4 USBRXFUNCADDR12(2) USB Receive Functional Address Endpoint 12 Go
0x0E6 USBRXHUBADDR12(2) USB Receive Hub Address Endpoint 12 Go
0x0E7 USBRXHUBPORT12(2) USB Receive Hub Port Endpoint 12 Go
0x0E8 USBTXFUNCADDR13(2) USB Transmit Functional Address Endpoint 13 Go
0x0EA USBTXHUBADDR13(2) USB Transmit Hub Address Endpoint 13 Go
0x0EB USBTXHUBPORT13(2) USB Transmit Hub Port Endpoint 13 Go
0x0EC USBRXFUNCADDR13(2) USB Receive Functional Address Endpoint 13 Go
0x0EE USBRXHUBADDR13(2) USB Receive Hub Address Endpoint 13 Go
0x0EF USBRXHUBPORT13(2) USB Receive Hub Port Endpoint 13 Go
0x0F0 USBTXFUNCADDR14(2) USB Transmit Functional Address Endpoint 14 Go
0x0F2 USBTXHUBADDR14(2) USB Transmit Hub Address Endpoint 14 Go
0x0F3 USBTXHUBPORT14(2) USB Transmit Hub Port Endpoint 14 Go
0x0F4 USBRXFUNCADDR14(2) USB Receive Functional Address Endpoint 14 Go
0x0F6 USBRXHUBADDR14(2) USB Receive Hub Address Endpoint 14 Go
0x0F7 USBRXHUBPORT14(2) USB Receive Hub Port Endpoint 14 Go
0x0F8 USBTXFUNCADDR15(2) USB Transmit Functional Address Endpoint 15 Go
0x0FA USBTXHUBADDR15(2) USB Transmit Hub Address Endpoint 15 Go
0x0FB USBTXHUBPORT15(2) USB Transmit Hub Port Endpoint 15 Go
0x0FC USBRXFUNCADDR15(2) USB Receive Functional Address Endpoint 15 Go
0x0FE USBRXHUBADDR15(2) USB Receive Hub Address Endpoint 15 Go
0x0FF USBRXHUBPORT15(2) USB Receive Hub Port Endpoint 15 Go
0x102 USBCSRL0(1)(2) USB Control and Status Endpoint 0 Low Go
0x103 USBCSRH0(1)(2) USB Control and Status Endpoint 0 High Go
0x108 USBCOUNT0(1)(2) USB Receive Byte Count Endpoint 0 Go
0x10A USBTYPE0(2) USB Type Endpoint 0 Go
0x10B USBNAKLMT(2) USB NAK Limit Go
0x110 USBTXMAXP1(1)(2) USB Maximum Transmit Data Endpoint 1 Go
0x112 USBTXCSRL1(1)(2) USB Transmit Control and Status Endpoint 1 Low Go
0x113 USBTXCSRH1(1)(2) USB Transmit Control and Status Endpoint 1 High Go
0x114 USBRXMAXP1(1)(2) USB Maximum Receive Data Endpoint 1 Go
0x116 USBRXCSRL1(1)(2) USB Receive Control and Status Endpoint 1 Low Go
0x117 USBRXCSRH1(1)(2) USB Receive Control and Status Endpoint 1 High Go
0x118 USBRXCOUNT1(1)(2) USB Receive Byte Count Endpoint 1 Go
0x11A USBTXTYPE1(2) USB Host Transmit Configure Type Endpoint 1 Go
0x11B USBTXINTERVAL1(2) USB Host Transmit Interval Endpoint 1 Go
0x11C USBRXTYPE1(2) USB Host Configure Receive Type Endpoint 1 Go
0x11D USBRXINTERVAL1(2) USB Host Receive Polling Interval Endpoint 1 Go
0x120 USBTXMAXP2(1)(2) USB Maximum Transmit Data Endpoint 2 Go
0x122 USBTXCSRL2(1)(2) USB Transmit Control and Status Endpoint 2 Low Go
0x123 USBTXCSRH2(1)(2) USB Transmit Control and Status Endpoint 2 High Go
0x124 USBRXMAXP2(1)(2) USB Maximum Receive Data Endpoint 2 Go
0x126 USBRXCSRL2(1)(2) USB Receive Control and Status Endpoint 2 Low Go
0x127 USBRXCSRH2(1)(2) USB Receive Control and Status Endpoint 2 High Go
0x128 USBRXCOUNT2(1)(2) USB Receive Byte Count Endpoint 2 Go
0x12A USBTXTYPE2(2) USB Host Transmit Configure Type Endpoint 2 Go
0x12B USBTXINTERVAL2(2) USB Host Transmit Interval Endpoint 2 Go
0x12C USBRXTYPE2(2) USB Host Configure Receive Type Endpoint 2 Go
0x12D USBRXINTERVAL2(2) USB Host Receive Polling Interval Endpoint 2 Go
0x130 USBTXMAXP3(1)(2) USB Maximum Transmit Data Endpoint 3 Go
0x132 USBTXCSRL3(1)(2) USB Transmit Control and Status Endpoint 3 Low Go
0x133 USBTXCSRH3(1)(2) USB Transmit Control and Status Endpoint 3 High Go
0x134 USBRXMAXP3(1)(2) USB Maximum Receive Data Endpoint 3 Go
0x136 USBRXCSRL3(1)(2) USB Receive Control and Status Endpoint 3 Low Go
0x137 USBRXCSRH3(1)(2) USB Receive Control and Status Endpoint 3 High Go
0x138 USBRXCOUNT3(1)(2) USB Receive Byte Count Endpoint 3 Go
0x13A USBTXTYPE3(2) USB Host Transmit Configure Type Endpoint 3 Go
0x13B USBTXINTERVAL3(2) USB Host Transmit Interval Endpoint 3 Go
0x13C USBRXTYPE3(2) USB Host Configure Receive Type Endpoint 3 Go
0x13D USBRXINTERVAL3(2) USB Host Receive Polling Interval Endpoint 3 Go
0x140 USBTXMAXP4(1)(2) USB Maximum Transmit Data Endpoint 4 Go
0x142 USBTXCSRL4(1)(2) USB Transmit Control and Status Endpoint 4 Low Go
0x143 USBTXCSRH4(1)(2) USB Transmit Control and Status Endpoint 4 High Go
0x144 USBRXMAXP4(1)(2) USB Maximum Receive Data Endpoint 4 Go
0x146 USBRXCSRL4(1)(2) USB Receive Control and Status Endpoint 4 Low Go
0x147 USBRXCSRH4(1)(2) USB Receive Control and Status Endpoint 4 High Go
0x148 USBRXCOUNT4(1)(2) USB Receive Byte Count Endpoint 4 Go
0x14A USBTXTYPE4(2) USB Host Transmit Configure Type Endpoint 4 Go
0x14B USBTXINTERVAL4(2) USB Host Transmit Interval Endpoint 4 Go
0x14C USBRXTYPE4(2) USB Host Configure Receive Type Endpoint 4 Go
0x14D USBRXINTERVAL4(2) USB Host Receive Polling Interval Endpoint 4 Go
0x150 USBTXMAXP5(1)(2) USB Maximum Transmit Data Endpoint 5 Go
0x152 USBTXCSRL5(1)(2) USB Transmit Control and Status Endpoint 5 Low Go
0x153 USBTXCSRH5(1)(2) USB Transmit Control and Status Endpoint 5 High Go
0x154 USBRXMAXP5(1)(2) USB Maximum Receive Data Endpoint 5 Go
0x156 USBRXCSRL5(1)(2) USB Receive Control and Status Endpoint 5 Low Go
0x157 USBRXCSRH5(1)(2) USB Receive Control and Status Endpoint 5 High Go
0x158 USBRXCOUNT5(1)(2) USB Receive Byte Count Endpoint 5 Go
0x15A USBTXTYPE5(2) USB Host Transmit Configure Type Endpoint 5 Go
0x15B USBTXINTERVAL5(2) USB Host Transmit Interval Endpoint 5 Go
0x15C USBRXTYPE5(2) USB Host Configure Receive Type Endpoint 5 Go
0x15D USBRXINTERVAL5(2) USB Host Receive Polling Interval Endpoint 5 Go
0x160 USBTXMAXP6(1)(2) USB Maximum Transmit Data Endpoint 6 Go
0x162 USBTXCSRL6(1)(2) USB Transmit Control and Status Endpoint 6 Low Go
0x163 USBTXCSRH6(1)(2) USB Transmit Control and Status Endpoint 6 High Go
0x164 USBRXMAXP6(1)(2) USB Maximum Receive Data Endpoint 6 Go
0x166 USBRXCSRL6(1)(2) USB Receive Control and Status Endpoint 6 Low Go
0x167 USBRXCSRH6(1)(2) USB Receive Control and Status Endpoint 6 High Go
0x168 USBRXCOUNT6(1)(2) USB Receive Byte Count Endpoint 6 Go
0x16A USBTXTYPE6(2) USB Host Transmit Configure Type Endpoint 6 Go
0x16B USBTXINTERVAL6(2) USB Host Transmit Interval Endpoint 6 Go
0x16C USBRXTYPE6(2) USB Host Configure Receive Type Endpoint 6 Go
0x16D USBRXINTERVAL6(2) USB Host Receive Polling Interval Endpoint 6 Go
0x170 USBTXMAXP7(1)(2) USB Maximum Transmit Data Endpoint 7 Go
0x172 USBTXCSRL7(1)(2) USB Transmit Control and Status Endpoint 7 Low Go
0x173 USBTXCSRH7(1)(2) USB Transmit Control and Status Endpoint 7 High Go
0x174 USBRXMAXP7(1)(2) USB Maximum Receive Data Endpoint 7 Go
0x176 USBRXCSRL7(1)(2) USB Receive Control and Status Endpoint 7 Low Go
0x177 USBRXCSRH7(1)(2) USB Receive Control and Status Endpoint 7 High Go
0x178 USBRXCOUNT7(1)(2) USB Receive Byte Count Endpoint 7 Go
0x17A USBTXTYPE7(2) USB Host Transmit Configure Type Endpoint 7 Go
0x17B USBTXINTERVAL7(2) USB Host Transmit Interval Endpoint 7 Go
0x17C USBRXTYPE7(2) USB Host Configure Receive Type Endpoint 7 Go
0x17D USBRXINTERVAL7(2) USB Host Receive Polling Interval Endpoint 7 Go
0x180 USBTXMAXP8(1)(2) USB Maximum Transmit Data Endpoint 8 Go
0x182 USBTXCSRL8(1)(2) USB Transmit Control and Status Endpoint 8 Low Go
0x183 USBTXCSRH8(1)(2) USB Transmit Control and Status Endpoint 8 High Go
0x184 USBRXMAXP8(1)(2) USB Maximum Receive Data Endpoint 8 Go
0x186 USBRXCSRL8(1)(2) USB Receive Control and Status Endpoint 8 Low Go
0x187 USBRXCSRH8(1)(2) USB Receive Control and Status Endpoint 8 High Go
0x188 USBRXCOUNT8(1)(2) USB Receive Byte Count Endpoint 8 Go
0x18A USBTXTYPE8(2) USB Host Transmit Configure Type Endpoint 8 Go
0x18B USBTXINTERVAL8(2) USB Host Transmit Interval Endpoint 8 Go
0x18C USBRXTYPE8(2) USB Host Configure Receive Type Endpoint 8 Go
0x18D USBRXINTERVAL8(2) USB Host Receive Polling Interval Endpoint 8 Go
0x190 USBTXMAXP9(1)(2) USB Maximum Transmit Data Endpoint 9 Go
0x192 USBTXCSRL9(1)(2) USB Transmit Control and Status Endpoint 9 Low Go
0x193 USBTXCSRH9(1)(2) USB Transmit Control and Status Endpoint 9 High Go
0x194 USBRXMAXP9(1)(2) USB Maximum Receive Data Endpoint 9 Go
0x196 USBRXCSRL9(1)(2) USB Receive Control and Status Endpoint 9 Low Go
0x197 USBRXCSRH9(1)(2) USB Receive Control and Status Endpoint 9 High Go
0x198 USBRXCOUNT9(1)(2) USB Receive Byte Count Endpoint 9 Go
0x19A USBTXTYPE9(2) USB Host Transmit Configure Type Endpoint 9 Go
0x19B USBTXINTERVAL9(2) USB Host Transmit Interval Endpoint 9 Go
0x19C USBRXTYPE9(2) USB Host Configure Receive Type Endpoint 9 Go
0x19D USBRXINTERVAL9(2) USB Host Receive Polling Interval Endpoint 9 Go
0x1A0 USBTXMAXP10(1)(2) USB Maximum Transmit Data Endpoint 10 Go
0x1A2 USBTXCSRL10(1)(2) USB Transmit Control and Status Endpoint 10 Low Go
0x1A3 USBTXCSRH10(1)(2) USB Transmit Control and Status Endpoint 10 High Go
0x1A4 USBRXMAXP10(1)(2) USB Maximum Receive Data Endpoint 10 Go
0x1A6 USBRXCSRL10(1)(2) USB Receive Control and Status Endpoint 10 Low Go
0x1A7 USBRXCSRH10(1)(2) USB Receive Control and Status Endpoint 10 High Go
0x1A8 USBRXCOUNT10(1)(2) USB Receive Byte Count Endpoint 10 Go
0x1AA USBTXTYPE10(2) USB Host Transmit Configure Type Endpoint 10 Go
0x1AB USBTXINTERVAL10(2) USB Host Transmit Interval Endpoint 10 Go
0x1AC USBRXTYPE10(2) USB Host Configure Receive Type Endpoint 10 Go
0x1AD USBRXINTERVAL10(2) USB Host Receive Polling Interval Endpoint 10 Go
0x1B0 USBTXMAXP11(1)(2) USB Maximum Transmit Data Endpoint 11 Go
0x1B2 USBTXCSRL11(1)(2) USB Transmit Control and Status Endpoint 11 Low Go
0x1B3 USBTXCSRH11(1)(2) USB Transmit Control and Status Endpoint 11 High Go
0x1B4 USBRXMAXP11(1)(2) USB Maximum Receive Data Endpoint 11 Go
0x1B6 USBRXCSRL11(1)(2) USB Receive Control and Status Endpoint 11 Low Go
0x1B7 USBRXCSRH11(1)(2) USB Receive Control and Status Endpoint 11 High Go
0x1B8 USBRXCOUNT11(1)(2) USB Receive Byte Count Endpoint 11 Go
0x1BA USBTXTYPE11(2) USB Host Transmit Configure Type Endpoint 11 Go
0x1BB USBTXINTERVAL11(2) USB Host Transmit Interval Endpoint 11 Go
0x1BC USBRXTYPE11(2) USB Host Configure Receive Type Endpoint 11 Go
0x1BD USBRXINTERVAL11(2) USB Host Receive Polling Interval Endpoint 11 Go
0x1C0 USBTXMAXP12(1)(2) USB Maximum Transmit Data Endpoint 12 Go
0x1C2 USBTXCSRL12(1)(2) USB Transmit Control and Status Endpoint 12 Low Go
0x1C3 USBTXCSRH12(1)(2) USB Transmit Control and Status Endpoint 12 High Go
0x1C4 USBRXMAXP12(1)(2) USB Maximum Receive Data Endpoint 12 Go
0x1C6 USBRXCSRL12(1)(2) USB Receive Control and Status Endpoint 12 Low Go
0x1C7 USBRXCSRH12(1)(2) USB Receive Control and Status Endpoint 12 High Go
0x1C8 USBRXCOUNT12(1)(2) USB Receive Byte Count Endpoint 12 Go
0x1CA USBTXTYPE12(2) USB Host Transmit Configure Type Endpoint 12 Go
0x1CB USBTXINTERVAL12(2) USB Host Transmit Interval Endpoint 12 Go
0x1CC USBRXTYPE12(2) USB Host Configure Receive Type Endpoint 12 Go
0x1CD USBRXINTERVAL12(2) USB Host Receive Polling Interval Endpoint 12 Go
0x1D0 USBTXMAXP13(1)(2) USB Maximum Transmit Data Endpoint 13 Go
0x1D2 USBTXCSRL13(1)(2) USB Transmit Control and Status Endpoint 13 Low Go
0x1D3 USBTXCSRH13(1)(2) USB Transmit Control and Status Endpoint 13 High Go
0x1D4 USBRXMAXP13(1)(2) USB Maximum Receive Data Endpoint 13 Go
0x1D6 USBRXCSRL13(1)(2) USB Receive Control and Status Endpoint 13 Low Go
0x1D7 USBRXCSRH13(1)(2) USB Receive Control and Status Endpoint 13 High Go
0x1D8 USBRXCOUNT13(1)(2) USB Receive Byte Count Endpoint 13 Go
0x1DA USBTXTYPE13(2) USB Host Transmit Configure Type Endpoint 13 Go
0x1DB USBTXINTERVAL13(2) USB Host Transmit Interval Endpoint 13 Go
0x1DC USBRXTYPE13(2) USB Host Configure Receive Type Endpoint 13 Go
0x1DD USBRXINTERVAL13(2) USB Host Receive Polling Interval Endpoint 13 Go
0x1E0 USBTXMAXP14(1)(2) USB Maximum Transmit Data Endpoint 14 Go
0x1E2 USBTXCSRL14(1)(2) USB Transmit Control and Status Endpoint 14 Low Go
0x1E3 USBTXCSRH14(1)(2) USB Transmit Control and Status Endpoint 14 High Go
0x1E4 USBRXMAXP14(1)(2) USB Maximum Receive Data Endpoint 14 Go
0x1E6 USBRXCSRL14(1)(2) USB Receive Control and Status Endpoint 14 Low Go
0x1E7 USBRXCSRH14(1)(2) USB Receive Control and Status Endpoint 14 High Go
0x1E8 USBRXCOUNT14(1)(2) USB Receive Byte Count Endpoint 14 Go
0x1EA USBTXTYPE14(2) USB Host Transmit Configure Type Endpoint 14 Go
0x1EB USBTXINTERVAL14(2) USB Host Transmit Interval Endpoint 14 Go
0x1EC USBRXTYPE14(2) USB Host Configure Receive Type Endpoint 14 Go
0x1ED USBRXINTERVAL14(2) USB Host Receive Polling Interval Endpoint 14 Go
0x1F0 USBTXMAXP15(1)(2) USB Maximum Transmit Data Endpoint 15 Go
0x1F2 USBTXCSRL15(1)(2) USB Transmit Control and Status Endpoint 15 Low Go
0x1F3 USBTXCSRH15(1)(2) USB Transmit Control and Status Endpoint 15 High Go
0x1F4 USBRXMAXP15(1)(2) USB Maximum Receive Data Endpoint 15 Go
0x1F6 USBRXCSRL15(1)(2) USB Receive Control and Status Endpoint 15 Low Go
0x1F7 USBRXCSRH15(1)(2) USB Receive Control and Status Endpoint 15 High Go
0x1F8 USBRXCOUNT15(1)(2) USB Receive Byte Count Endpoint 15 Go
0x1FA USBTXTYPE15(2) USB Host Transmit Configure Type Endpoint 15 Go
0x1FB USBTXINTERVAL15(2) USB Host Transmit Interval Endpoint 15 Go
0x1FC USBRXTYPE15(2) USB Host Configure Receive Type Endpoint 15 Go
0x1FD USBRXINTERVAL15(2) USB Host Receive Polling Interval Endpoint 15 Go
0x304 USBRQPKTCOUNT1(2) USB Request Packet Count in Block Transfer Endpoint 1 Go
0x308 USBRQPKTCOUNT2(2) USB Request Packet Count in Block Transfer Endpoint 2 Go
0x30C USBRQPKTCOUNT3(2) USB Request Packet Count in Block Transfer Endpoint 3 Go
0x310 USBRQPKTCOUNT4(2) USB Request Packet Count in Block Transfer Endpoint 4 Go
0x314 USBRQPKTCOUNT5(2) USB Request Packet Count in Block Transfer Endpoint 5 Go
0x318 USBRQPKTCOUNT6(2) USB Request Packet Count in Block Transfer Endpoint 6 Go
0x31C USBRQPKTCOUNT7(2) USB Request Packet Count in Block Transfer Endpoint 7 Go
0x320 USBRQPKTCOUNT8(2) USB Request Packet Count in Block Transfer Endpoint 8 Go
0x324 USBRQPKTCOUNT9(2) USB Request Packet Count in Block Transfer Endpoint 9 Go
0x328 USBRQPKTCOUNT10(2) USB Request Packet Count in Block Transfer Endpoint 10 Go
0x32C USBRQPKTCOUNT11(2) USB Request Packet Count in Block Transfer Endpoint 11 Go
0x330 USBRQPKTCOUNT12(2) USB Request Packet Count in Block Transfer Endpoint 12 Go
0x334 USBRQPKTCOUNT13(2) USB Request Packet Count in Block Transfer Endpoint 13 Go
0x338 USBRQPKTCOUNT14(2) USB Request Packet Count in Block Transfer Endpoint 14 Go
0x33C USBRQPKTCOUNT15(2) USB Request Packet Count in Block Transfer Endpoint 15 Go
0x340 USBRXDPKTBUFDIS(1)(2) USB Receive Double Packet Buffer Disable Go
0x342 USBTXDPKTBUFDIS(1)(2) USB Transmit Double Packet Buffer Disable Go
0x400 USBEPC(1)(2) USB External Power Control Go
0x404 USBEPCRIS(1)(2) USB External Power Control Raw Interrupt Status Go
0x408 USBEPCIM(2)(1) USB External Power Control Interrupt Mask Go
0x40C USBEPCISC(1)(2) USB External Power Control Interrupt Status and Clear Go
0x410 USBDRRIS(1)(2) USB Device RESUME Raw Interrupt Status Go
0x414 USBDRIM(1)(2) USB Device RESUME Interrupt Mask Go
0x418 USBDRISC(1)(2) USB Device RESUME Interrupt Status and Clear Go
0x41C USBGPCS(1)(2) USB General-Purpose Control and Status Go
0x450 USBDMASEL(1)(2) USB DMA Select Go
(1) This register is used in Device mode. Some registers are used for both Host and Device mode and can have different bit definitions depending on the mode.
(2) This register is used in Host mode. Some registers are used for both Host and Device mode and can have different bit definitions depending on the mode. The USB controller is in Device mode upon reset, so the reset values shown for these registers apply to the Device mode definition.