SPRUJ81 February   2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1

 

  1.   Trademarks
  2. 1 Introduction
  3. 2 Width/Spacing Proposal for Escapes
  4. 3 Stackup
  5. 4 Via Sharing
  6. 5 Floorplan Component Placement
  7. 6 Critical Interfaces Impact Placement
  8. 7 Routing Priority
  9. 8 SerDes Interfaces
  10. 9 DDR Interfaces
  11. 10Power Decoupling
  12. 11Route Lowest Priority Interfaces Last
  13. 12Summary

11 Route Lowest Priority Interfaces Last

When the length matching and simulations for high speed interfaces and DDR have been completed for the highest priority interfaces and the Power Distribution Network (PDN) analysis has been completed, then the layout can continue with the medium and then the lower priority interfaces.