SPRZ491D december   2020  – june 2023 DRA821U , DRA821U-Q1

 

  1.   1
  2. 1Modules Affected
  3. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  4. 3Silicon Revision 1.0, 2.0 Usage Notes and Advisories
    1. 3.1 Silicon Revision 1.0, 2.0 Usage Notes
    2. 3.2 Silicon Revision 1.0, 2.0 Advisories
    3.     i2049
    4.     i2062
    5.     i2091
    6.     i2116
    7.     i2123
    8. 3.3 i2126
    9. 3.4 i2127
    10.     i2134
    11.     i2137
    12.     i2146
    13. 3.5 i2151
    14.     i2157
    15.     i2159
    16.     i2160
    17.     i2161
    18.     i2163
    19.     i2166
    20.     i2177
    21.     i2182
    22.     i2183
    23.     i2184
    24.     i2185
    25.     i2186
    26.     i2187
    27.     i2189
    28.     i2196
    29.     i2197
    30.     i2201
    31.     i2205
    32.     i2207
    33.     i2208
    34.     i2209
    35.     i2216
    36.     i2217
    37.     i2221
    38.     i2222
    39.     i2227
    40.     i2228
    41.     i2232
    42.     i2234
    43.     i2235
    44.     i2237
    45.     i2241
    46.     i2242
    47.     i2243
    48.     i2244
    49.     i2245
    50.     i2246
    51.     i2249
    52.     i2253
    53.     i2257
    54.     i2274
    55.     i2275
    56.     i2277
    57.     i2278
    58.     i2279
    59.     i2283
    60.     i2306
    61.     i2307
    62.     i2310
    63.     i2311
    64.     i2312
    65.     i2320
    66.     i2326
    67.     i2329
    68.     i2351
    69.     i2360
    70.     i2361
    71.     i2362
    72.     i2366
    73.     i2371
    74.     i2372
    75.     i2383
  5.   Trademarks
  6.   Revision History

Revision History

Changes from September 1, 2022 to June 10, 2023 (from Revision C (September 2022) to Revision D (June 2023))

  • Added Advisory i2151; ADC: Debounce time control registerGo
  • Added Advisory i2221; CC: Invasive and Non-Invasive debug enable settings are reset by MCU_RESETzGo
  • Added Advisory i2222; Compute Cluster: A72 Corepac unable to be powered downGo
  • Updated Description and Workaround for i2227; R5FSS: Error interrupt CCM_COMPARE_STAT_PULSE_INTR incorrectly driven.Go
  • Added Advisory i2243; PCIe: Timing requirement for disabling output refclk during L1.2 substate is not metGo
  • Added i2246; PCIe: Automatic compliance entry fails when unused SERDES lanes are not assigned to PCIe ControllerGo
  • Added Advisory i2249; OSPI: Internal PHY Loopback and Internal Pad Loopback clocking modes with DDR timing inoperableGo
  • Added Advisory i2253; PRG: CTRL_MMR STAT registers are unreliable indicators of POK threshold failureGo
  • Added Advisory i2274; DDR: Including DDR in BSCAN causes current alarm on the DDR supplyGo
  • Added Advisory i2275; DMSC Secure Boot ROM: Potential Secure Boot vulnerability with explicit EC curve parameters in X.509 certificateGo
  • Added Advisory i2283; Restrictions on how CP Tracer Debug Probes can be usedGo
  • Added Advisory i2306; ROM Code: Need to turn off internal termination resistors in SERDESGo
  • Added Advisory i2312; MMCSD: HS200 and SDR104 Command Timeout Window Too SmallGo
  • Added Advisory i2326; PCIe: MAIN_PLLx operating in fractional mode, which is required for enabling SSC, is not compliant with PCIe Refclk jitter limitsGo
  • Added Usage Note i2351; OSPI: Controller does not support Continuous Read mode with NAND FlashGo
  • Added Advisory i2360; Boot: Ethernet RMII Boot Mode is not supportedGo
  • Added Advisory i2361; Boot: SPI and xSPI BOOTMODE Pin Mapping changes for SR2.0Go
  • Added Advisory i2362; 10-100M SGMII: Marvell PHY does not ignore the preamble byte resulting in link failureGo
  • Added Advisory i2366; Boot: ROM does not comprehend specific JEDEC SFDP features for 8D-8D-8D operationGo
  • Added Advisory i2371; Boot: ROM code may hang in UART boot mode during data transferGo
  • Added Usage Note i2372; Boot: ROM doesn't support select multi-plane addressing schemes in Serial NAND bootGo
  • Added Advisory i2383; OSPI: 2-byte address is not supported in PHY DDR modeGo