SPVA022 July   2025 SN65176B , SN75176B

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Motivation
  6. 3 Feature
  7. 4 Cover Tape Peeling Strength
  8. 5 Electrostatic Charges
  9. 6 Multi-Row Carrier Tape Design
  10. 7 Device Name Nomenclature
  11. 8 What I Need to do on my SMT Equipment?
  12. 9 Conclusion
  13. 10Additional Resources

6 Multi-Row Carrier Tape Design

Pin1 Orientation and Sealing Line Figure 6-1 Pin1 Orientation and Sealing Line
SOIC and TSSOP Configuration SOIC and TSSOP Configuration Figure 6-2 SOIC and TSSOP Configuration
Table 6-1 SOIC and TSSOP Tape and Reel Guideline
Package Group Pins and Package Designator Rows Tape Width W (mm) Pocket Pitch (mm) Pin1 Quadrant (see Figure 6-1) Units per Reel Reel Size (Inches) F1 F2 F3
SOIC 8D 3 24 8 Q1 7500 13 5.25 6.25 6.25
TSSOP 8PW 3 24 8 Q1 9000 13 5.25 6.25 6.25
TSSOP 14/16PW 3 24 8 Q1 9000 13 5.05 6.45 6.45