TIDUES0E June   2019  – April 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Highlighted Products
      1. 2.2.1  UCC21710
      2. 2.2.2  UCC14141-Q1
      3. 2.2.3  AMC1311
      4. 2.2.4  AMC1302
      5. 2.2.5  OPA320
      6. 2.2.6  AMC1306M05
      7. 2.2.7  AMC1336
      8. 2.2.8  TMCS1133
      9. 2.2.9  TMS320F280039C
      10. 2.2.10 TLVM13620
      11. 2.2.11 ISOW1044
      12. 2.2.12 TPS2640
    3. 2.3 System Design Theory
      1. 2.3.1 Dual Active Bridge Analogy With Power Systems
      2. 2.3.2 Dual-Active Bridge – Switching Sequence
      3. 2.3.3 Dual-Active Bridge – Zero Voltage Switching (ZVS)
      4. 2.3.4 Dual-Active Bridge - Design Considerations
        1. 2.3.4.1 Leakage Inductor
        2. 2.3.4.2 Soft Switching Range
        3. 2.3.4.3 Effect of Inductance on Current
        4. 2.3.4.4 Phase Shift
        5. 2.3.4.5 Capacitor Selection
          1. 2.3.4.5.1 DC-Blocking Capacitors
        6. 2.3.4.6 Switching Frequency
        7. 2.3.4.7 Transformer Selection
        8. 2.3.4.8 SiC MOSFET Selection
      5. 2.3.5 Loss Analysis
        1. 2.3.5.1 SiC MOSFET and Diode Losses
        2. 2.3.5.2 Transformer Losses
        3. 2.3.5.3 Inductor Losses
        4. 2.3.5.4 Gate Driver Losses
        5. 2.3.5.5 Efficiency
        6. 2.3.5.6 Thermal Considerations
  9. 3Circuit Description
    1. 3.1 Power Stage
    2. 3.2 DC Voltage Sensing
      1. 3.2.1 Primary DC Voltage Sensing
      2. 3.2.2 Secondary DC Voltage Sensing
        1. 3.2.2.1 Secondary Side Battery Voltage Sensing
    3. 3.3 Current Sensing
    4. 3.4 Power Architecture
      1. 3.4.1 Auxiliary Power Supply
      2. 3.4.2 Gate Driver Bias Power Supply
      3. 3.4.3 Isolated Power Supply for Sense Circuits
    5. 3.5 Gate Driver Circuit
    6. 3.6 Additional Circuitry
    7. 3.7 Simulation
      1. 3.7.1 Setup
      2. 3.7.2 Running Simulations
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Required Hardware and Software
      1. 4.1.1 Hardware
      2. 4.1.2 Software
        1. 4.1.2.1 Getting Started With Software
        2. 4.1.2.2 Pin Configuration
        3. 4.1.2.3 PWM Configuration
        4. 4.1.2.4 High-Resolution Phase Shift Configuration
        5. 4.1.2.5 ADC Configuration
        6. 4.1.2.6 ISR Structure
    2. 4.2 Test Setup
    3. 4.3 PowerSUITE GUI
    4. 4.4 LABs
      1. 4.4.1 Lab 1
      2. 4.4.2 Lab 2
      3. 4.4.3 Lab 3
      4. 4.4.4 Lab 4
      5. 4.4.5 Lab 5
      6. 4.4.6 Lab 6
      7. 4.4.7 Lab 7
    5. 4.5 Test Results
      1. 4.5.1 Closed-Loop Performance
  11. 5Design Files
    1. 5.1 Schematics
    2. 5.2 Bill of Materials
    3. 5.3 Altium Project
    4. 5.4 Gerber Files
    5. 5.5 Assembly Drawings
  12. 6Related Documentation
    1. 6.1 Trademarks
  13. 7Terminology
  14. 8About the Author
  15. 9Revision History

Lab 2

In the lab 2 build, the board is excited in open-loop fashion with a specified frequency (100 kHz) and phase shift. The phase shift can be changed through the watch window. The phase shift is controlled with the DAB_pwmPhaseShiftPrimSec_pu variable. This build verifies the sensing of feedback values from the power stage, operation of the PWM gate driver, HW protection, and makes sure there are no hardware issues. Additionally, calibrate the input and output voltage sensing in this build. For the HW test setup see Section 4.2.

  • Software Setup for Lab 2

    The following defines are set in the settings.h file for this build. The settings can be defined by selecting Lab 2: Open Loop PWM with Protection in the drop-down menu of Project Options from PowerSUITE GUI.

    TIDA-010054 Lab 2 Software
                            Setup Figure 4-20 Lab 2 Software Setup
    1. Run the project by clicking the green run button in CCS.
    2. Populate the required variables in the watch window by loading JavaScript setupdebugenv_lab2.js in the scripting console.
      TIDA-010054 Lab 2 Watch
                                    View Configuration Figure 4-21 Lab 2 Watch View Configuration
    3. In the watch view, check if the DAB_vPrimSensed_Volts, DAB_iPrimSensed_Amps, DAB_vSecSensed_Volts, and DAB_iSecSensed_Amps variables are updating periodically.
      Note: Because no power is applied at this point, these variables are close to zero.
  • Relay and fan validation

    • In idle state the auxiliary 12-V power supply needs to consume approximately 700 mA.
    • Write a "1" to DAB_enableRelay. The typical clicking is usually audible and the current consumption needs to increase to approximately 1.14 A.
    • Write a "1" to DAB_enableFan. The fans start spinning and the current consumption increases to 1.43 A (here two CFM6015V-154-362 fans are used).
  • Power transfer validation
    • Apply a low-input voltage (for example, 50 V)
    • Clear PWM trip by writing "1" into DAB_clear trip
    • Verify that voltage and current appear on the output
    • Phase shift can be varied by modifying DAB_pwmPhaseShuftPrimSecRef_pu

    By default, the DAB_pwmPhaseShiftPrimSec_pu variable is set to 0.02. Vary this phase shift slowly in steps of 0.002 pu and observe the change in voltage at the output of the converter. Make sure to not increase the phase shift very high as the phase shift can boost the output voltage greater than the input voltage and can lead to breakdown of MOSFETs at the maximum applied voltage.

  • Protection validation

    Before actual high-voltage and high-power testing, validate the protection features. Validation can also be done at low voltages (for example, 50-V input). The limits for overcurrent and overvoltage protection can be modified from PowerSUITE GUI, see Figure 4-9.

    1. Primary overcurrent protection:
      1. Set IPRIM_TRIP to 1 A
      2. Connect 50-V input voltage
      3. Enable relays and clear PWM
      4. Increase phase shift step by step to increase primary current
      5. Observe trip after 1 A is crossed
      TIDA-010054 Lab 2 -
                                    Primary Overcurrent Protection
      Primary - overcurrent protection, limit set = 1 A
      Figure 4-22 Lab 2 - Primary Overcurrent Protection
    2. Primary tank overcurrent protection
      1. Set IPRIM_TANK_TRIP to 1.5 A
      2. Connect 50-V input voltage
      3. Enable relays and clear PWM
      4. Increase phase shift step by step to increase primary tank current
      5. Observe trip after 1.5 A is crossed
      TIDA-010054 Lab 2 -
                                    Primary Tank Overcurrent Protection
      Primary - tank overcurrent protection, limit set = 1.5 A
      Figure 4-23 Lab 2 - Primary Tank Overcurrent Protection
    3. Secondary overcurrent protection
      1. Set ISEC_TRIP to 1.5 A
      2. Connect 50-V input voltage
      3. Enable relays and clear PWM
      4. Increase phase shift step by step to increase secondary current
      5. Observe trip after 1.5 A is crossed
      TIDA-010054 LAB 2 -
                                    Secondary Overcurrent Protection Figure 4-24 LAB 2 - Secondary Overcurrent Protection
    4. Secondary overvoltage protection
      1. Set VSEC_TRIP to 40 V
      2. Connect 50-V input voltage
      3. Enable relays and clear PWM
      4. Increase phase shift step by step to increase secondary voltage
      5. Observe trip after 40 V is crossed
      TIDA-010054 LAB 2 -
                                    Overvoltage Protection Figure 4-25 LAB 2 - Overvoltage Protection

      The previous waveforms show PWM is shut off by the comparator subsystem during fault events. The type of fault is displayed in the watch window through variable DAB_tripFlag, see Figure 4-26. The trip can be reset by selecting noTrip under the drop-down menu and re-enabling the PWM by writing “1” to the DAB_clearTrip variable. Make sure the fault condition is removed before re-enabling the PWM.

TIDA-010054 Trip Indication in Expression
                    Window Figure 4-26 Trip Indication in Expression Window
  • Measure SFRA Plant for Voltage Loop
    1. The SFRA is integrated in the C2000Ware-DigitalPower-SDK kit to measure the plant response which can then be used to design a compensator. Run the SFRA by clicking on the SFRA icon. The SFRA GUI opens.
    2. Select the options for the device on the SFRA GUI; for example, for F280039, select floating point. Click the Setup Connection button. In the pop-up window, uncheck the boot-on-connect option and select an appropriate COM port. Select the OK button. Return to the SFRA GUI and click the Connect button.
    3. The SFRA GUI connects to the device. A SFRA sweep can now be started by clicking the Start Sweep button. The complete SFRA sweep takes a few minutes to complete. Monitor the activity in the progress bar on the SFRA GUI or by checking the flashing blue LED on the back of the control card, which indicates UART activity.
      TIDA-010054 Lab 2 SFRA
                                    Plant Plot for the Open Voltage Loop Test
      Test Condition: VIN = 800 V, VOUT = 500 V, IOUT = 10 A, phase shift = 0.047 pu.
      Noise in the phase plot is expected for higher frequencies due to noise in the output voltage measurement and small plant gain.
      Figure 4-27 Lab 2 SFRA Plant Plot for the Open Voltage Loop Test
    4. The Frequency Response Data SFRA.csv is saved in the project folder, under an SFRA Data Folder, and is time-stamped with the time of the SFRA run. SFRA can be run at different frequency setpoints to cover the range of operation of the system. A compensator is designed using these measured plots through compensator designer. Compensation designer can be opened from the main.syscfg GUI.

      Inside ISR1, the SFRA injects small signal perturbations in phase and observes the sensed output voltage variations. The following lines of code inside the dab.h file perform the SFRA signal injection and collection.

      TIDA-010054 Lab 2 Code for
                                    SFRA Signal Injection Figure 4-28 Lab 2 Code for SFRA Signal Injection
  • Measure SFRA Plant for Current Loop
    1. Follow the same steps as in voltage loop to get started with SFRA measurement for current loop.
    2. In the PowerSUITE GUI under SFRA tab, choose current prior to running the SFRA current loop.
      TIDA-010054 Lab 2 Code
                                    Defines SFRA Current Loop Figure 4-29 Lab 2 Code Defines SFRA Current Loop
    3. Inside ISR1, the SFRA injects small signal perturbations in phase and observes the sensed output current variations. The following lines of code inside the dab.h file perform the SFRA signal injection and collection.
      TIDA-010054 Lab 2 Code for
                                    SFRA Signal Injection Figure 4-30 Lab 2 Code for SFRA Signal Injection
    4. Measure the plant response from SFRA GUI. The open loop and plant response are stored in the file named SFRA.csv. Use this file to tune the compensator for the current loop.
      TIDA-010054 Lab 2 SFRA
                                    Plant Plot for the Open Current Loop Test
      Test Condition: VIN = 800 V, VOUT = 500 V, IOUT = 10 A, phase shift = 0.047 pu
      Figure 4-31 Lab 2 SFRA Plant Plot for the Open Current Loop Test