DLPS167A March   2024  – September 2024 DLPC964

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input High-Speed Serial (HSS) Interface
      2. 6.3.2 Block Interface
      3. 6.3.3 Control Interface
        1. 6.3.3.1 Watchdog
        2. 6.3.3.2 LOAD2
          1. 6.3.3.2.1 LOAD2 Row Addressing
          2. 6.3.3.2.2 LOAD2 Block Clears
        3. 6.3.3.3 Receiver Low Power Mode Enable
        4. 6.3.3.4 DMD High Speed Serial Interface (HSSI) Reset
        5. 6.3.3.5 DMD Power Enable
      4. 6.3.4 User K-Data Interface
      5. 6.3.5 Status Interface
        1. 6.3.5.1 INIT_DONE
        2. 6.3.5.2 MCP_ACTIVE
        3. 6.3.5.3 BLKLOADZ
        4. 6.3.5.4 High-Speed Serial Interface (HSSI) Bus Error
        5. 6.3.5.5 IRQZ
      6. 6.3.6 Reset, System Clock, and Power Good
        1. 6.3.6.1 Controller Reset
        2. 6.3.6.2 Main Oscillator Clock
        3. 6.3.6.3 DMD HSSI Bus Oscillator Clock
        4. 6.3.6.4 POWERGOOD and DMDPOWERGOOD
      7. 6.3.7 I2C Interface
        1. 6.3.7.1 Configuration Pins
        2. 6.3.7.2 Communications Interface
          1. 6.3.7.2.1 Command Format
      8. 6.3.8 DMD (HSSI) Interface
        1. 6.3.8.1 Park Control
        2. 6.3.8.2 Configurable HSSI Settings
      9. 6.3.9 Flash PROM Interface
        1. 6.3.9.1 JTAG Interface
    4. 6.4 Device Functional Modes
      1. 6.4.1 DLPC964 Aurora 64B/66B Input Data and Command Write Cycle
        1. 6.4.1.1 Block Mode Operation (Block Start with Block Control Word)
          1. 6.4.1.1.1 Block Clear and Block Set
          2. 6.4.1.1.2 Image Orientation—Block Load Increment / Decrement
          3. 6.4.1.1.3 Single Channel Mode
        2. 6.4.1.2 DMD Bit Plane Data Input (Quad Input Mode)
        3. 6.4.1.3 DMD Bit Plane Data Input (Single Input Mode)
        4. 6.4.1.4 Block Complete (DMDLOAD_REQ and BLKLOADZ)
      2. 6.4.2 DMD Row Operation
      3. 6.4.3 Block Load Address Select
      4. 6.4.4 Block Mode Select
      5. 6.4.5 Mirror Clocking Pulse (MCP)
    5. 6.5 Register Map
      1. 6.5.1 Register Table Overview
        1. 6.5.1.1  FPGA_INTERRUPT_STATUS Register
        2. 6.5.1.2  FPGA_INTERRUPT_ENABLE_CONTROL Register
        3. 6.5.1.3  FPGA_MAIN_STATUS Register
        4. 6.5.1.4  FPGA_VERSION Register
        5. 6.5.1.5  FPGA_MAIN_CTRL Register
        6. 6.5.1.6  SELF_TEST_REG Register
        7. 6.5.1.7  DMDIF_ERROR_STATUS_CLR Register
        8. 6.5.1.8  DMDIF_ERROR_STATUS Register
        9. 6.5.1.9  PRBS7_MACRO0_TEST_RESULT Register
        10. 6.5.1.10 PRBS7_MACRO1_TEST_RESULT Register
        11. 6.5.1.11 PRBS7_MACRO2_TEST_RESULT Register
        12. 6.5.1.12 PRBS7_MACRO3_TEST_RESULT Register
        13. 6.5.1.13 PRBS7_TEST_CONTROL Register
        14. 6.5.1.14 PRBS7_TEST_RUNSTATUS Register
        15. 6.5.1.15 LS_BUS_TEST_RESULT Register
        16. 6.5.1.16 DMD_TYPE Register
        17. 6.5.1.17 HSS_RESET Register
        18. 6.5.1.18 HSS_CHANNEL_STATUS Register
        19. 6.5.1.19 HSS_LANE_STATUS Register
        20. 6.5.1.20 HSS_CH0_SOFTERROR_COUNT Register
        21. 6.5.1.21 HSS_CH1_SOFTERROR_COUNT Register
        22. 6.5.1.22 HSS_CH2_SOFTERROR_COUNT Register
        23. 6.5.1.23 HSS_CH3_SOFTERROR_COUNT Register
        24. 6.5.1.24 HSS_SOFTERROR_COUNT_RESET Register
        25. 6.5.1.25 HSSI_Channel_0_DMD_Data_GT_Cell_Control Register
        26. 6.5.1.26 HSSI_Channel_0_DMD_Clock_GT_Cell_Control Register
        27. 6.5.1.27 HSSI_Channel_1_DMD_Data_GT_Cell_Control Register
        28. 6.5.1.28 HSSI_Channel_1_DMD_Clock_GT_Cell_Control Register
        29. 6.5.1.29 HSSI_Channel_2_DMD_Data_GT_Cell_Control Register
        30. 6.5.1.30 HSSI_Channel_2_DMD_Clock_GT_Cell_Control Register
        31. 6.5.1.31 HSSI_Channel_3_DMD_Data_GT_Cell_Control Register
        32. 6.5.1.32 HSSI_Channel_3_DMD_Clock_GT_Cell_Control Register
        33. 6.5.1.33 HSSI_DMD_Vcm_Value Register
        34. 6.5.1.34 TEST_DMD_ID Register
        35. 6.5.1.35 TEST_DMD_FUSE1 Register
        36. 6.5.1.36 TEST_DMD_FUSE2 Register
        37. 6.5.1.37 TEST_DMD_FUSE3 Register
        38. 6.5.1.38 TEST_DMD_FUSE4 Register
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 High Speed Direct Imaging Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
      4. 7.2.4 DMD Mirror Switching Performance Plots
    3. 7.3 Interfacing to DLPC964 Controller High Speed Serial (HSS) Aurora 64B/66B Inputs
      1. 7.3.1 Theory of Operation
        1. 7.3.1.1 Block Start with Block Control Word
        2. 7.3.1.2 Block Complete with DMDLOAD_REQ
        3. 7.3.1.3 DMDLOAD_REQ Setup Time Requirement
        4. 7.3.1.4 Single Channel Transfer Mode
        5. 7.3.1.5 DMD Block Array Data Mapping
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power Supply Distribution and Requirements
      2. 7.4.2 Power Down Requirements
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 PCB Design Standards
        2. 7.5.1.2 Signal Layers
        3. 7.5.1.3 General PCB Routing
          1. 7.5.1.3.1 Trace Minimum Spacing
          2. 7.5.1.3.2 Trace Length Matching
            1. 7.5.1.3.2.1 HSSI Output Bus Skew
            2. 7.5.1.3.2.2 Aurora 64B/66B Input Bus Skew
              1. 7.5.1.3.2.2.1 Other Timing Critical Signals
          3. 7.5.1.3.3 Trace Impedance and Routing Priority
      2. 7.5.2 Power and Ground Planes
      3. 7.5.3 Power Vias
      4. 7.5.4 Decoupling
    6. 7.6 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.4.5 Mirror Clocking Pulse (MCP)

A Mirror Clocking Pulse (MCP) sequence begins by setting BLKMODE_[1:0] and BLKADDR_[3:0] for a single, dual, quad, or global block operation. When asserted, MCP_Start causes an MCP on the block(s), and the data stored in the block(s) takes effect on the mirrors of the DMD. Shortly after an MCP is issued, MCPn_ACTIVE goes high, indicating an MCP operation is in progress. During this time, no additional MCPs may be initiated until MCPn_ACTIVE returns low. A typical single block load phased sequence in which consecutive DMD blocks are loaded is illustrated in Figure 6-5. An MCP time is identical for single, dual, quad, or global block operations.

It may take longer to complete an MCP on a block than it does to load a block. The single block load time for the DLP991U DMD is outlined in Table 6-8.

Table 6-8 DMD Overview
DMD ARRAY MIRROR SETTLING TIME (μs) SINGLE ROW LOAD TIME (ns) SINGLE BLOCK LOAD TIME (μs) GLOBAL RESET MODE FULL ARRAY (PATTERNS/SECOND) QUAD BLOCK RESET MODE FULL ARRAY (PATTERNS/SECOND)
DLP991U 4096 × 2176 4 37.09 5.04 11,273 12,390

See Section 7.3.1.3 for input data timing description and requirements for any case which involves sending an MCP, block clear, or block set without data loading.

DLPC964 Single Block Load Phased Sequence Figure 6-5 Single Block Load Phased Sequence

To fully utilize the DMD bandwidth, load four blocks and then concurrently issue an MCP to the four blocks by setting BLKMODE_[1:0] to 10 and BLKADDR_[3:0] to the proper address for the four blocks being reset. This is illustrated in Figure 6-7.

DLPC964 Dual Block Load Phased Sequence Figure 6-6 Dual Block Load Phased Sequence
DLPC964 Quad Block Load Phased Sequence Figure 6-7 Quad Block Load Phased Sequence

It is possible to load other blocks while the block(s) previously issued an MCP is settling. This is illustrated in Figure 6-6 and Figure 6-7, where blocks are reloaded while the mirror settling time is occurring. It is also possible to load other blocks while previously loaded block(s) have an outstanding MCPn_ACTIVE. This is illustrated in Figure 6-7, where block 0 is loaded while MCPn_ACTIVE is asserted for blocks 12–15.

The DLPC964 controller handles all timing activities related to the Mirror Clocking Pulse, including setup and hold timing to reset of each block, the reset waveform generation timing, and any constraints on loading, clearing, fast clearing, or resetting adjacent or non-adjacent blocks. The DLPC964 controller holds off from accepting loading or clearing commands for a specific block while an MCP is in progress.