DLPS170 Data sheet

DLPS170C September 2020 – January 2025 DLP471TE

PRODUCTION DATA

5.4 Recommended Operating Conditions

Over operating free-air temperature range and supply voltages (unless otherwise noted). The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the Recommended Operating Conditions limits.

		MIN	TYP	MAX	UNIT
SUPPLY VOLTAGES⁽¹⁾⁽²⁾
V_DD	Supply voltage for LVCMOS core logic and low speed interface (LSIF)	1.71	1.8	1.95	V
V_DDA	Supply voltage for high speed serial interface (HSSI) receivers	1.71	1.8	1.95	V
V_OFFSET	Supply voltage for HVCMOS and micromirror electrode⁽³⁾	9.5	10	10.5	V
V_BIAS	Supply voltage for micromirror electrode	17.5	18	18.5	V
V_RESET	Supply voltage for micromirror electrode	–14.5	–14	–13.5	V
\| V_DDA – V_DD \|	Supply voltage delta, absolute value⁽⁴⁾			0.3	V
\| V_BIAS – V_OFFSET \|	Supply voltage delta, absolute value⁽⁵⁾			10.5	V
\| V_BIAS – V_RESET \|	Supply voltage delta, absolute value			33	V
LVCMOS INPUT
V_IH	High level input voltage ⁽⁶⁾	0.7 × V_DD			V
V_IL	Low level input voltage⁽⁶⁾			0.3 × V_DD	V
LOW SPEED SERIAL INTERFACE (LSIF)
f_CLOCK	LSIF clock frequency (LS_CLK)⁽⁷⁾	108	120	130	MHz
DCD_IN	LSIF duty cycle distortion (LS_CLK)	44%		56%
\| V_ID \|	LSIF differential input voltage magnitude⁽⁷⁾	150	350	440	mV
V_LVDS	LSIF voltage⁽⁷⁾	575		1520	mV
V_CM	Common mode voltage⁽⁷⁾	700	900	1300	mV
Z_LINE	Line differential impedance (PWB/trace)	90	100	110	Ω
Z_IN	Internal differential termination resistance	80	100	120	Ω
HIGH SPEED SERIAL INTERFACE (HSSI)
f_CLOCK	HSSI clock frequency (DCLK)⁽⁸⁾	1.2		1.6	GHz
DCD_IN	HSSI duty cycle distortion (DCLK)	44%	50%	56%
\| V_ID \| Data	HSSI differential input voltage magnitude data lane⁽⁸⁾	100		600	mV
\| V_ID \| CLK	HSSI differential input voltage magnitude Clock lane⁽⁸⁾	295		600	mV
VCM_DC Data	Input common mode voltage (DC) data lane⁽⁸⁾	200	600	800	mV
VCM_DC CLK	Input common mode voltage (DC) Clk lane⁽⁸⁾	200	600	800	mV
VCM_ACp-p	AC peak to peak (ripple) on common mode voltage of data lane and Clock lane⁽⁸⁾			100	mV
Z_LINE	Line differential impedance (PWB/trace)		100		Ω
Z_IN	Internal differential termination resistance (R_Xterm)	80	100	120	Ω
ENVIRONMENTAL
T_ARRAY	Array temperature, long–term operational⁽⁹⁾⁽¹⁰⁾⁽¹²⁾	10		40 to 70 ⁽¹¹⁾	°C
T_ARRAY	Array temperature, short-term operational, 500 hr max⁽¹⁰⁾⁽¹³⁾	0		10	°C
T_WINDOW	Window temperature, operational⁽¹⁴⁾⁽¹⁸⁾			85	°C
\|T_DELTA\|	Absolute temperature delta between any point on the window edge and the ceramic test point TP1⁽¹⁵⁾			14	°C
T_DP-AVG	Average dew point temperature (non-condensing)⁽¹⁶⁾			28	°C
T_DP-ELR	Elevated dew point temperature range (non-condensing)⁽¹⁷⁾	28		36	°C
CT_ELR	Cumulative time in elevated dew point temperature range			24	months
ILL_θ	Illumination marginal ray angle⁽¹⁸⁾⁽¹⁸⁾			55	degrees
SOLID STATE ILLUMINATION
ILL_UV	Illumination power at wavelengths < 410nm⁽⁹⁾⁽²⁰⁾			10	mW/cm2
ILL_VIS	Illumination power at wavelengths ≥ 410nm and ≤ 800nm ⁽¹⁹⁾⁽²⁰⁾			44.9	W/cm2
ILL_IR	Illumination power at wavelengths > 800nm⁽²⁰⁾			10	mW/cm2
ILL_BLU	Illumination power at wavelengths ≥ 410nm and ≤ 475nm⁽¹⁹⁾⁽²⁰⁾			14.3	W/cm2
ILL_BLU1	Illumination power at wavelengths ≥ 410nm and ≤ 440nm ⁽¹⁹⁾⁽²⁰⁾			2.3	W/cm2
LAMP ILLUMINATION
ILL_UV	Illumination power at wavelengths < 395nm⁽⁹⁾⁽²⁰⁾			2.0	mW/cm2
ILL_VIS	Illumination power at wavelengths ≥ 395nm and ≤ 800nm⁽¹⁹⁾⁽²⁰⁾			36.8	W/cm2
ILL_IR	Illumination power at wavelengths > 800nm⁽²⁰⁾			10	mW/cm2

(1) All power supply connections are required to operate the DMD: V_DD, V_DDA, V_OFFSET, V_BIAS, and V_RESET. All V_SS connections are required to operate the DMD.

(2) All voltage values are with respect to the V_SS ground pins.

(3) V_OFFSET supply transients must fall within specified max voltages.

(4) To prevent excess current, the supply voltage delta | V_DDA – V_DD | must be less than specified limit.

(5) To prevent excess current, the supply voltage delta | V_BIAS – V_OFFSET | must be less than specified limit.

(6) LVCMOS input pin is DMD_DEN_ARSTZ.

(7) See the low speed interface (LSIF) timing requirements in Timing Requirements.

(8) See the high speed serial interface (HSSI) timing requirements in Timing Requirements.

(9) Simultaneous exposure of the DMD to the maximum Section 5.4 for temperature and UV illumination reduces device lifetime.

(10) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point (TP1) shown in Figure 6-1 and the Section 5.5 using the Section 6.6.

(11) Per Figure 5-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to the Section 6.8 for a definition of micromirror landed duty cycle.

(12) Long-term is defined as the usable life of the device.

(13) Short-term is the total cumulative time over the useful life of the device.

(14) The locations of thermal test points TP2, TP3, TP4, and TP5 shown in the DMD Thermal Test Points are intended to measure the highest window edge
temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular
application causes additional points on the window edge to be at a higher temperature, test points should be added to those locations.

(15) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in DMD Thermal Test Points. The window test points TP2, TP3, TP4, and TP5 shown in DMD Thermal Test Points are intended to result in the worst case delta temperature. If a particular application causes another point on the window edge to result in a larger delta in temperature, that point should be used.

(16) The average over time (including storage and operating) that the device is not in the ‘elevated dew point temperature range'.

(17) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CT_ELR.

(18) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including pond of micromirrors (POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM) will contribute to thermal limitations described in this document, and may negatively affect lifetime.

(19) The maximum allowable optical power incident on the DMD is limited by the maximum optical power density for each wavelength range specified and the micromirror array temperature (T_ARRAY).

(20) To calculate, see the Micromirror Power Density Calculation.

DLP471TE Maximum Recommended Array
Temperature—Derating Curve

Figure 5-1 Maximum Recommended Array Temperature—Derating Curve