DLPS254 January   2026 DLP390TP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5.     11
    6. 5.5  Thermal Information
    7. 5.6  Electrical Characteristics
    8. 5.7  Switching Characteristics
    9. 5.8  Timing Requirements
    10.     16
    11. 5.9  System Mounting Interface Loads
    12. 5.10 Micromirror Array Physical Characteristics
    13. 5.11 Micromirror Array Optical Characteristics
    14. 5.12 Window Characteristics
    15. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 LPSDR Low-Speed Interface
      3. 6.3.3 High-Speed Interface
      4. 6.3.4 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Window Aperture Illumination Overfill Calculation
    9. 6.9 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.9.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.9.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.9.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.9.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Temperature Sensor Diode
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. 9 Layout
    1. 9.1 Layout Guidelines
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

DLP390TP FQZ Package 159-Pin LGA (Bottom View) Figure 4-1 FQZ Package 159-Pin LGA (Bottom View)
Table 4-1 Pin Functions
PIN(2) TYPE(1) DESCRIPTION TERMINATION TRACE LENGTH (mm)
NAME PAD ID
D_AP(0) C7 I High-Speed Differential Data Pair lane A0 Differential 100Ω 3.927
D_AN(0) D7 I High-Speed Differential Data Pair lane A0 Differential 100Ω 4.265
D_AP(1) D5 I High-Speed Differential Data Pair lane A1 Differential 100Ω 2.565
D_AN(1) D6 I High-Speed Differential Data Pair lane A1 Differential 100Ω 2.902
D_AP(2) E3 I High-Speed Differential Data Pair lane A2 Differential 100Ω 0.543
D_AN(2) E4 I High-Speed Differential Data Pair lane A2 Differential 100Ω 0.881
D_AP(3) D1 I High-Speed Differential Data Pair lane A3 Differential 100Ω 2.015
D_AN(3) D2 I High-Speed Differential Data Pair lane A3 Differential 100Ω 2.352
D_AP(4) F6 I High-Speed Differential Data Pair lane A4 Differential 100Ω 3.19
D_AN(4) F7 I High-Speed Differential Data Pair lane A4 Differential 100Ω 3.526
D_AP(5) F5 I High-Speed Differential Data Pair lane A5 Differential 100Ω 2.123
D_AN(5) G5 I High-Speed Differential Data Pair lane A5 Differential 100Ω 2.456
D_AP(6) G3 I High-Speed Differential Data Pair lane A6 Differential 100Ω 0.829
D_AN(6) G4 I High-Speed Differential Data Pair lane A6 Differential 100Ω 1.162
D_AP(7) H7 I High-Speed Differential Data Pair lane A7 Differential 100Ω 3.856
D_AN(7) G7 I High-Speed Differential Data Pair lane A7 Differential 100Ω 4.189
DCLK_AP E5 I High-Speed Differential Clock A Differential 100Ω 2.23
DCLK_AN E6 I High-Speed Differential Clock A Differential 100Ω 2.562
D_BP(0) B25 I High-Speed Differential Data Pair lane B0 Differential 100Ω 2.825
D_BN(0) B24 I High-Speed Differential Data Pair lane B0 Differential 100Ω 3.158
D_BP(1) D25 I High-Speed Differential Data Pair lane B1 Differential 100Ω 1.636
D_BN(1) D24 I High-Speed Differential Data Pair lane B1 Differential 100Ω 1.972
D_BP(2) D21 I High-Speed Differential Data Pair lane B2 Differential 100Ω 2.278
D_BN(2) D20 I High-Speed Differential Data Pair lane B2 Differential 100Ω 2.611
D_BP(3) C24 I High-Speed Differential Data Pair lane B3 Differential 100Ω 3.099
D_BN(3) C23 I High-Speed Differential Data Pair lane B3 Differential 100Ω 3.439
D_BP(4) E21 I High-Speed Differential Data Pair lane B4 Differential 100Ω 2.687
D_BN(4) E20 I High-Speed Differential Data Pair lane B4 Differential 100Ω 3.022
D_BP(5) F22 I High-Speed Differential Data Pair lane B5 Differential 100Ω 1.323
D_BN(5) F21 I High-Speed Differential Data Pair lane B5 Differential 100Ω 1.658
D_BP(6) G23 I High-Speed Differential Data Pair lane B6 Differential 100Ω 0.821
D_BN(6) G22 I High-Speed Differential Data Pair lane B6 Differential 100Ω 1.162
D_BP(7) G21 I High-Speed Differential Data Pair lane B7 Differential 100Ω 2.173
D_BN(7) G20 I High-Speed Differential Data Pair lane B7 Differential 100Ω 2.506
DCLK_BP E23 I High-Speed Differential Clock B Differential 100Ω 0.865
DCLK_BN E22 I High-Speed Differential Clock B Differential 100Ω 1.202
D_CP(0) J6 I High-Speed Differential Data Pair lane C0 Differential 100Ω 3.463
D_CN(0) H6 I High-Speed Differential Data Pair lane C0 Differential 100Ω 3.795
D_CP(1) K6 I High-Speed Differential Data Pair lane C1 Differential 100Ω 3.703
D_CN(1) K7 I High-Speed Differential Data Pair lane C1 Differential 100Ω 4.035
D_CP(2) J2 I High-Speed Differential Data Pair lane C2 Differential 100Ω 1.461
D_CN(2) J3 I High-Speed Differential Data Pair lane C2 Differential 100Ω 1.759
D_CP(3) L1 I High-Speed Differential Data Pair lane C3 Differential 100Ω 2.409
D_CN(3) K1 I High-Speed Differential Data Pair lane C3 Differential 100Ω 2.742
D_CP(4) L6 I High-Speed Differential Data Pair lane C4 Differential 100Ω 3.15
D_CN(4) L7 I High-Speed Differential Data Pair lane C4 Differential 100Ω 3.492
D_CP(5) N1 I High-Speed Differential Data Pair lane C5 Differential 100Ω 3.341
D_CN(5) N2 I High-Speed Differential Data Pair lane C5 Differential 100Ω 3.679
D_CP(6) N6 I High-Speed Differential Data Pair lane C6 Differential 100Ω 3.564
D_CN(6) N7 I High-Speed Differential Data Pair lane C6 Differential 100Ω 3.898
D_CP(7) K2 I High-Speed Differential Data Pair lane C7 Differential 100Ω 1.022
D_CN(7) K3 I High-Speed Differential Data Pair lane C7 Differential 100Ω 1.361
DCLK_CP M5 I High-Speed Differential Clock C Differential 100Ω 3.428
DCLK_CN L5 I High-Speed Differential Clock C Differential 100Ω 3.82
D_DP(0) H21 I High-Speed Differential Data Pair lane D0 Differential 100Ω 3.035
D_DN(0) H20 I High-Speed Differential Data Pair lane D0 Differential 100Ω 3.369
D_DP(1) H23 I High-Speed Differential Data Pair lane D1 Differential 100Ω 0.894
D_DN(1) H22 I High-Speed Differential Data Pair lane D1 Differential 100Ω 1.231
D_DP(2) J22 I High-Speed Differential Data Pair lane D2 Differential 100Ω 1.791
D_DN(2) J21 I High-Speed Differential Data Pair lane D2 Differential 100Ω 2.13
D_DP(3) K25 I High-Speed Differential Data Pair lane D3 Differential 100Ω 2.037
D_DN(3) K24 I High-Speed Differential Data Pair lane D3 Differential 100Ω 2.372
D_DP(4) K21 I High-Speed Differential Data Pair lane D4 Differential 100Ω 2.203
D_DN(4) K20 I High-Speed Differential Data Pair lane D4 Differential 100Ω 2.543
D_DP(5) L25 I High-Speed Differential Data Pair lane D5 Differential 100Ω 2.72
D_DN(5) M25 I High-Speed Differential Data Pair lane D5 Differential 100Ω 3.052
D_DP(6) N24 I High-Speed Differential Data Pair lane D6 Differential 100Ω 2.997
D_DN(6) N23 I High-Speed Differential Data Pair lane D6 Differential 100Ω 3.335
D_DP(7) N21 I High-Speed Differential Data Pair lane D7 Differential 100Ω 4.046
D_DN(7) N20 I High-Speed Differential Data Pair lane D7 Differential 100Ω 4.338
DCLK_DP L21 I High-Speed Differential Clock D Differential 100Ω 3.658
DCLK_DN L20 I High-speed Differential Clock D Differential 100Ω 4.045
MBRST(0) NC Mirrormirror voltage for Reset Block 0 6.16289
MBRST(1) NC Mirrormirror voltage for Reset Block 1 3.93281
MBRST(2) NC Mirrormirror voltage for Reset Block 2 6.10819
MBRST(3) NC Mirrormirror voltage for Reset Block 3 3.42259
MBRST(4) NC Mirrormirror voltage for Reset Block 4 4.31038
TP0 K23 I 10 HVia Chain 5.71246
TP1 L23 I 2 MVia Chain 4.99283
TP2 M23 I Humidity Sensor 4.82511
TEMP_N N4 I Temp Diode N 1.70894
TEMP_P N3 I Temp Diode P 1.7438
LS_RDATA_D C3 O LPSDR Output 0.55459
LS_RDATA_C C1 O LPSDR Output 1.39057
LS_WDATA B5 I LPSDR Input 1.97914
LS_RDATA_B B2 O LPSDR Output 0.98339
LS_RDATA_A A3 O LPSDR Output 1.42875
LS_CLK A4 I LPSDR Input 1.55589
DMD_DEN_ARSTZ D3 I ARSTZ 17.5kΩ pulldown 0.9734
VDD

A2, A5, A7,

A21, A23,

A25, B1,

B20, B22,

C4, C5,

C22, E2,

F4, J5, K4,

K22, L3,

L23, M4,

M6, M21,

M22, N25

 P Digital Core Supply Voltage Plane
VBIAS A6, B21 P Supply Voltage for Positive Bias of Micromirror reset signal Plane
VRESET B6, C21 P Supply Voltage for Negative Bias of Micromirror reset signal Plane
VOFFSET C6, L22 P Supply voltage for HVCMOS logic,stepped up logic level Plane
VDDI

B3, B23,

K23, M1,

M3, M24

 P Plane
VSS

A1, A20,

A22, A24,

B4, B7, C2,

C20, C25,

D4, D22,

D23, E7,

F3, F20,

F23, G6,

H3, H4, H5,

J4, J7, J20,

J23, K5,

L2, L4,

L24, M2,

M7, M20,

M23, N5,

N22

 G Ground Plane
N/C

B17, C18,

B18, C19,

B19, M17,

M19, M18

 NC No Connect Pin None
(1) I=Input, O=Output, P=Power, G=Ground, NC=No Connect
(2) Only 143 pins are electrically connected for functional use.