DLPS308A June   2025  – October 2025 DLPC6422

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Recommended Operating Conditions
    3. 5.3  Thermal Information
    4. 5.4  Electrical Characteristics
    5. 5.5  ESD Ratings
    6. 5.6  System Oscillators Timing Requirements
    7. 5.7  Test and Reset Timing Requirements
    8. 5.8  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    9. 5.9  Port 1 Input Pixel Timing Requirements
    10. 5.10 Port 3 Input Pixel Interface (through GPIO) Timing Requirements
    11. 5.11 DMD LVDS Interface Timing Requirements
    12. 5.12 Synchronous Serial Port (SSP) Interface Timing Requirements
    13. 5.13 Programmable Output Clocks Switching Characteristics
    14. 5.14 Synchronous Serial Port Interface (SSP) Switching Characteristics
    15. 5.15 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 System Reset Operation
        1. 6.3.1.1 Power-Up Reset Operation
        2. 6.3.1.2 System Reset Operation
      2. 6.3.2 Spread Spectrum Clock Generator Support
      3. 6.3.3 GPIO Interface
      4. 6.3.4 Source Input Blanking
      5. 6.3.5 Video Graphics Processing Delay
      6. 6.3.6 Program Memory Flash/SRAM Interface
      7. 6.3.7 Calibration and Debug Support
      8. 6.3.8 Board Level Test Support
    4. 6.4 Device Functional Modes
      1. 6.4.1 Standby Mode
      2. 6.4.2 Active Mode
        1. 6.4.2.1 Normal Configuration
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 Recommended MOSC Crystal Oscillator Configuration
      2. 7.2.2 Detailed Design Procedure
    3. 7.3 Power Supply Requirements and Recommendations
      1. 7.3.1 System Power Regulations
      2. 7.3.2 System Power-Up Sequence
      3. 7.3.3 Power-On Sense (POSENSE) Support
      4. 7.3.4 System Environment and Defaults
        1. 7.3.4.1 DLPC6422 System Power-Up and Reset Default Conditions
        2. 7.3.4.2 1.1V 1.15V System Power
        3. 7.3.4.3 1.8V System Power
        4. 7.3.4.4 3.3V System Power
        5. 7.3.4.5 Power Good (PWRGOOD) Support
        6. 7.3.4.6 5V Tolerant Support
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 PCB Layout Guidelines for Internal DLPC6422 Power
        2. 7.4.1.2 PCB Layout Guidelines for Auto-Lock Performance
        3. 7.4.1.3 DMD Interface Considerations
        4. 7.4.1.4 Layout Example
        5. 7.4.1.5 Thermal Considerations
  9. 8 Device and Documentation Support
    1. 8.1 Third-Party Products Disclaimer
    2. 8.2 Device Support
      1. 8.2.1 Video Timing Parameter Definitions
      2. 8.2.2 Device Nomenclature
      3. 8.2.3 Device Nomenclature
      4. 8.2.4 Device Markings
        1. 8.2.4.1 Device Marking
    3. 8.3 Documentation Support
      1. 8.3.1 Related Documentation
    4. 8.4 Receiving Notification of Documentation Updates
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.3.8 Board Level Test Support

The in-circuit tristate enable signal (ICTSEN) is a board-level test control signal. By driving ICTSEN to a logic high state, all controller outputs (except TDO1 and TDO2) are tristated.

The DLPC6422 controller also provides JTAG boundary scan support on all I/O except non-digital I/O and a few special signals. Table 6-7 defines these exceptions.

Table 6-7 DLPC6422—Signals Not Covered by JTAG
SIGNAL NAMEPKG BALL
HW_TEST_ENM25
MOSCM26
MOSCNN26
USB_DAT_NC5
USB_DAT_PD6
TCKN24
TDIN25
TRSTZM23
TDO1N23
TDO2N22
TMS1P25
TMS2P26