DLPU106A March   2021  – October 2021 DLP3021-Q1

 

  1.   Abstract
  2. 1Trademarks
  3. 2DLP3021-Q1 Electronics EVM Overview
    1. 2.1 Introduction
    2. 2.2 What is in the DLP3021-Q1 Light Engine EVM
      1. 2.2.1 Formatter Subsystem
      2. 2.2.2 Illumination Subsystem
      3. 2.2.3 Light Engine
      4. 2.2.4 Cables
    3. 2.3 Non-Optical Specifications
      1. 2.3.1 Electrical Specifications
      2. 2.3.2 Component Temperature Ratings
      3. 2.3.3 LED Driver Design
      4. 2.3.4 Video Specification
  4. 3Quick Start
    1. 3.1 Kit Assembly Instructions
    2. 3.2 Software Installation
    3. 3.3 Power-Up
    4. 3.4 Select Display Content
    5. 3.5 LED Driver
  5. 4Optics and Mechanics
  6. 5Software
    1. 5.1 DLP Composer
      1. 5.1.1 Default Register Configuration
      2. 5.1.2 Illumination
      3. 5.1.3 Sequence Set
      4. 5.1.4 Degamma Curves
      5. 5.1.5 Image/Video
      6. 5.1.6 Flash Blocks
      7. 5.1.7 Flash Programming
    2. 5.2 DLP Control Program
      1. 5.2.1 Connection
      2. 5.2.2 Scripting
      3. 5.2.3 Registers
      4. 5.2.4 Commands
    3. 5.3 MSP430 Example Code
  7. 6Revision History

2.3.4 Video Specification

In this architecture, video content is compressed and stored in external flash memory. Low speed SPI commands are sent from the MSP430 MCU in Local Host Control operating mode or FTDI interface in Host Mute operating mode to the DMD controller to indicate what image/video content to read from the external 2Gb flash memory. Storing the image/video content in memory removes the need for a high-speed video interface to the module which improves compatibility with typical vehicle infrastructures. It also decreases overall system size and cost by removing graphics generation and interfaces. The controller decompresses each bit plane of the video data (608 × 684 resolution) and displays them on the DMD in rapid succession to create the full video image at a frame rate of 25 Hz. A frame rate of 25 Hz is recommended due to memory constraints, but the DLP3021-Q1 can support a maximum frame rate of 60 Hz. Due to the diamond format of the DMD pixels, the output image has an effective resolution of 864 × 480. The controller synchronizes the DMD bit plane data with the RGB enable timing for the LED color controller and driver circuit.