DLPU106A March   2021  – October 2021 DLP3021-Q1

 

  1.   Abstract
  2. 1Trademarks
  3. 2DLP3021-Q1 Electronics EVM Overview
    1. 2.1 Introduction
    2. 2.2 What is in the DLP3021-Q1 Light Engine EVM
      1. 2.2.1 Formatter Subsystem
      2. 2.2.2 Illumination Subsystem
      3. 2.2.3 Light Engine
      4. 2.2.4 Cables
    3. 2.3 Non-Optical Specifications
      1. 2.3.1 Electrical Specifications
      2. 2.3.2 Component Temperature Ratings
      3. 2.3.3 LED Driver Design
      4. 2.3.4 Video Specification
  4. 3Quick Start
    1. 3.1 Kit Assembly Instructions
    2. 3.2 Software Installation
    3. 3.3 Power-Up
    4. 3.4 Select Display Content
    5. 3.5 LED Driver
  5. 4Optics and Mechanics
  6. 5Software
    1. 5.1 DLP Composer
      1. 5.1.1 Default Register Configuration
      2. 5.1.2 Illumination
      3. 5.1.3 Sequence Set
      4. 5.1.4 Degamma Curves
      5. 5.1.5 Image/Video
      6. 5.1.6 Flash Blocks
      7. 5.1.7 Flash Programming
    2. 5.2 DLP Control Program
      1. 5.2.1 Connection
      2. 5.2.2 Scripting
      3. 5.2.3 Registers
      4. 5.2.4 Commands
    3. 5.3 MSP430 Example Code
  7. 6Revision History

2.2.2 Illumination Subsystem

The illumination subsystem includes the LED driver circuit and RGB LEDs. The FPGA has three PWM outputs which typically correspond to red, green, and blue illumination colors. The PWM duty cycles can be adjusted to set a reference voltage to an external illumination driver circuit as needed to balance colors and adjust output brightness. Typical illumination configurations for the DLP3021Q1EVM:

  • Optimal Color: PWM=450 with duty cycles of Red=30%, Green=45%, Blue=25%

  • High Brightness: PWM=450 with duty cycles of Red=24.9%, Green=62.4%, Blue=12.7%

The PWM is a 10-bit value that is initialized to the Default Register Configuration value of DLP Composer, but can be modified in real-time during display operation. The duty cycle of each RGB can only be configured in DLP Composer as part of a list of Sequence Settings.