SBAA415 April   2020 PCM6240-Q1 , PCM6260-Q1 , PCM6340-Q1 , PCM6360-Q1

 

  1.   Multiple PCM6xx0 Devices With Shared TDM and I2C Bus
    1.     Trademarks
    2. 1 Introduction
    3. 2 Sharing the Control Bus
    4. 3 Sharing the Audio Bus
      1. 3.1 ASI Configuration for Shared TDM
      2. 3.2 ASI Configuration for Daisy Chain TDM
    5. 4 Configuring PurePath Console for Multiple PCM6xx0 EVMs
      1. 4.1 Changing the Default I2C Address of the PCM6xx0 EVM
      2. 4.2 Launching PurePath Console With Multiple Devices
  2.   A PurePath Console I2C Scripts
    1.     A.1 PCM6xx0 I2C Scripts for Shared TDM
    2.     A.2 PCM6xx0 I2C Scripts for Daisy Chain TDM

Introduction

For PCM6xx0 applications requiring more than the channels supported by a single device, multiple PCM6xx0 devices can share a common bus. For systems with up to 16 analog input channels, up to four PCM6x40 devices can share a single control and audio data bus to minimize board routing area. For systems with up to 24 analog input channels, up to four PCM6x60 devices can share a single control and audio data bus to minimize board routing area. PCM6xx0 supports a control bus using the I2C interface and an audio serial bus using a time-division multiplexed (TDM), Inter-IC Sound (I2S), or Left-justified (LJ) interface. Figure 1 shows a diagram of four PCM6xx0 devices sharing the control and audio data buses.

bus-01-pcm6240-sbas884.gifFigure 1. Four PCM6xx0 Devices With Shared Control and Audio Data Buses

Each channel of the PCM6xx0 device follows the signal chain shown in Figure 2. Each channel of the PCM6xx0 supports an analog differential or single-ended signal. In PCM6xx0 device families, the analog input signal is amplified by a Programmable Gain Amplifier (PGA) and then converted by a high performance ADC into a digital signal. The PGA gains the input signal to match the full scale of the ADC. The digital signal has a programmable phase calibration to adjust the phase delay of each channel in steps of one modulator clock cycle. This allows the system to match the phase across different channels. The phase calibrated digital signal is then decimated through a set of linear phase filters or low latency filters. DC offset is removed from the decimated signal through a Digital High Pass Filter (HPF) with three pre-set cutoff frequencies or a fully programmable cutoff frequency. Note that DC shifts are caused by mismatches in common-mode voltages. The output of the HPF is gain calibrated with 0.1-dB steps and summed with other channels. The gain calibration matches the gain across different channels, particularly if the channels have microphones with varying gain values. The output is then filtered by the Digital Biquad Filters and gained by the volume control.

signalflow-01-pcm6240-sbas884.gifFigure 2. PCM6xx0 Channel Signal Chain Processing Flow Chart

This application note concentrates on how to configure the PCM6xx0 to share a single control and audio data bus between the devices.