For I2S-based digital audio communication protocols, the controller device generates the clocks: bit clock (BCLK) and word clock (WCLK) (or frame synchronization, FSYNC). Conversely, a target device receives the clocks: BCLK and WCLK (or FSYNC) from an external device. In many applications, a host processor with an advanced digital audio interface can act as the audio bus controller with the PCM6xx0 as a target device. However, having the audio ADC as the audio bus controller is advantageous in the following circumstances:
The following sections describe the modes, input parameters, or register settings required to configure the device as an audio bus controller.