SBAA457 June   2021 PCM6240-Q1 , PCM6260-Q1 , PCM6340-Q1 , PCM6360-Q1

 

  1.   Trademarks
  2.   Note
  3. 1Introduction
  4. 2Controller Mode
    1. 2.1 Controller Mode Configuration Options
      1. 2.1.1 Auto Clock Configuration With PLL Enabled
        1. 2.1.1.1 Supported Sample-Rates
        2. 2.1.1.2 Example 12-MHz MCLK
      2. 2.1.2 Auto Clock Detect With PLL Disabled
        1. 2.1.2.1 Supported Sample-Rates
        2. 2.1.2.2 Example
  5. 3Edge Sync for I2S and LJF in Controller Mode
    1. 3.1 Compatibility With Non-zero Offset
    2. 3.2 I2S Compatibility With Zero Offset (I2S only)

2 Controller Mode

For I2S-based digital audio communication protocols, the controller device generates the clocks: bit clock (BCLK) and word clock (WCLK) (or frame synchronization, FSYNC). Conversely, a target device receives the clocks: BCLK and WCLK (or FSYNC) from an external device. In many applications, a host processor with an advanced digital audio interface can act as the audio bus controller with the PCM6xx0 as a target device. However, having the audio ADC as the audio bus controller is advantageous in the following circumstances:

  • The host processor or DSP cannot output or generate standard audio clocks. A standard audio clock is an integer multiple of the sample rate that generates the necessary audio serial interface (ASI) FSYNC and BCLK clocks. In this case, an external PLL multiplier generates the appropriate audio clocks.
  • To easily synchronize multiple PCM6xx0 devices for simultaneous recording across all channels and devices. In this case, one PCM6xx0 device is configured as a controller to generate low-jitter ASI clocks.
  • The host does not have a flexible TDM/ASI bus to generate system required audio clocks, but allows these clocks as input when configured as a target device.

The following sections describe the modes, input parameters, or register settings required to configure the device as an audio bus controller.