SBAA457 June   2021 PCM6240-Q1 , PCM6260-Q1 , PCM6340-Q1 , PCM6360-Q1

 

  1.   Trademarks
  2.   Note
  3. 1Introduction
  4. 2Controller Mode
    1. 2.1 Controller Mode Configuration Options
      1. 2.1.1 Auto Clock Configuration With PLL Enabled
        1. 2.1.1.1 Supported Sample-Rates
        2. 2.1.1.2 Example 12-MHz MCLK
      2. 2.1.2 Auto Clock Detect With PLL Disabled
        1. 2.1.2.1 Supported Sample-Rates
        2. 2.1.2.2 Example
  5. 3Edge Sync for I2S and LJF in Controller Mode
    1. 3.1 Compatibility With Non-zero Offset
    2. 3.2 I2S Compatibility With Zero Offset (I2S only)

3.1 Compatibility With Non-zero Offset

If the system can accommodate an additional offset for I2S or LJF format, the addition of an non-zero offset to the ASI bus of PCM6xx0 device allows compliance to either standard. If used in a system with other audio devices, these other devices would also need to accommodate this offset. To add a non-zero offset, configure the following registers:

  • BCLK_POL (Page 0, ASI_CFG0 Register 0x07, Bit 2) = 1
  • TX_EDGE (Page 0, ASI_CFG0 Register 0x07, Bit 1) = 1

These settings change the base offset from the I2S and LJF formats to 1. Additional offsets can be achieved by using the TX_OFFSET (Page 0, ASI_CFG1 Register 0x08, Bits 4-0).